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authorNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>2018-11-29 01:39:48 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2018-12-07 11:45:03 +0100
commite2f4dd1f5b51b4dab813aa6e4db44e87aa750393 (patch)
treeb4837e16c5be92a0d23c1292d8ae25e1ae220e50 /drivers/clk/renesas/rcar-gen3-cpg.c
parentclk: renesas: rcar-gen3: Set state when registering SD clocks (diff)
downloadlinux-dev-e2f4dd1f5b51b4dab813aa6e4db44e87aa750393.tar.xz
linux-dev-e2f4dd1f5b51b4dab813aa6e4db44e87aa750393.zip
clk: renesas: rcar-gen3: Add documentation for SD clocks
Document the known use cases of the different clock settings. This is useful as different SoC and ES versions use different settings to do the same thing as there is more than one combination to achieve the same SDn clock speed. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/rcar-gen3-cpg.c')
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 6033bacd25f6..7782ec198df2 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -232,13 +232,13 @@ struct sd_clock {
* sd_srcfc sd_fc div
* stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
*-------------------------------------------------------------------
- * 0 0 0 (1) 1 (4) 4
- * 0 0 1 (2) 1 (4) 8
- * 1 0 2 (4) 1 (4) 16
- * 1 0 3 (8) 1 (4) 32
+ * 0 0 0 (1) 1 (4) 4 : SDR104 / HS200 / HS400 (8 TAP)
+ * 0 0 1 (2) 1 (4) 8 : SDR50
+ * 1 0 2 (4) 1 (4) 16 : HS / SDR25
+ * 1 0 3 (8) 1 (4) 32 : NS / SDR12
* 1 0 4 (16) 1 (4) 64
* 0 0 0 (1) 0 (2) 2
- * 0 0 1 (2) 0 (2) 4
+ * 0 0 1 (2) 0 (2) 4 : SDR104 / HS200 / HS400 (4 TAP)
* 1 0 2 (4) 0 (2) 8
* 1 0 3 (8) 0 (2) 16
* 1 0 4 (16) 0 (2) 32