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authorGeert Uytterhoeven <geert+renesas@glider.be>2017-07-19 17:39:54 +0200
committerGeert Uytterhoeven <geert+renesas@glider.be>2017-08-16 09:51:47 +0200
commit696997e004d4179f462d2ebd3efeb12a7cec5ef7 (patch)
tree61f14f2eafb16020aac087c1e5354980eec1aea8 /drivers/clk/renesas/renesas-cpg-mssr.c
parentclk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3 (diff)
downloadlinux-dev-696997e004d4179f462d2ebd3efeb12a7cec5ef7.tar.xz
linux-dev-696997e004d4179f462d2ebd3efeb12a7cec5ef7.zip
clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks
On R-Car Gen3 SoCs with a Spread Spectrum Clock Generator (e.g. R-Car D3), a peripheral clock divider has been added, to select between clean and spread spectrum parents. Add a new clock type to the R-Car Gen3 driver core to handle this. To avoid increasing the size of struct cpg_core_clk, both parents and dividers are stored in the existing parent resp. div fields. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/renesas/renesas-cpg-mssr.c')
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