diff options
| author |   Wolfram Sang <wsa+renesas@sang-engineering.com> | 2016-03-30 16:58:18 +0200 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2016-04-06 09:48:37 +0200 |
| commit | 5d3927f655e58e644557a3dc8ee7af8884f59931 (patch) | |
| tree | 72a8c57e260b79794e6444e86898c08c04c87176 /drivers/clk/renesas/renesas-cpg-mssr.h | |
| parent | clk: renesas: r8a7795: make SD clk definition specific for GEN3 (diff) | |
| download | linux-dev-5d3927f655e58e644557a3dc8ee7af8884f59931.tar.xz linux-dev-5d3927f655e58e644557a3dc8ee7af8884f59931.zip | |
clk: renesas: cpg-mssr: add generic support for read-only DIV6 clocks
Gen3 has two clocks (OSC and R) which look like a DIV6 clock but their
divider value is read-only and depends on MD pins at bootup. Add support
for such clocks by reading the value and adding a fixed clock.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/renesas-cpg-mssr.h')
| -rw-r--r-- | drivers/clk/renesas/renesas-cpg-mssr.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index cad3c7d1b0c6..0d1e3e811e79 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -37,6 +37,7 @@ enum clk_types { CLK_TYPE_IN, /* External Clock Input */ CLK_TYPE_FF, /* Fixed Factor Clock */ CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */ + CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */ /* Custom definitions start here */ CLK_TYPE_CUSTOM, @@ -53,6 +54,8 @@ enum clk_types { DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) #define DEF_DIV6P1(_name, _id, _parent, _offset) \ DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset) +#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ + DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1) /* * Definitions of Module Clocks |