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| author |   Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2019-03-07 22:53:19 +0300 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2019-04-02 10:31:05 +0200 |
| commit | 21ab095cbc069a351fa9cef919f2dafc43a8fde7 (patch) | |
| tree | 576eec4a8aacf56f1383d06154768ed6d3fcf293 /drivers/clk/renesas | |
| parent | clk: renesas: rcar-gen3: Rename DRIF clocks (diff) | |
| download | linux-dev-21ab095cbc069a351fa9cef919f2dafc43a8fde7.tar.xz linux-dev-21ab095cbc069a351fa9cef919f2dafc43a8fde7.zip | |
clk: renesas: r8a77980: Fix RPC-IF module clock's parent
Testing has shown that the RPC-IF module clock's parent is the RPCD2
clock, not the RPC one -- the RPC-IF register reads stall otherwise...
Fixes: 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r8a77980-cpg-mssr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c index f9e07fcc0d96..7227f675e61f 100644 --- a/drivers/clk/renesas/r8a77980-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c @@ -171,7 +171,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = { DEF_MOD("gpio1", 911, R8A77980_CLK_CP), DEF_MOD("gpio0", 912, R8A77980_CLK_CP), DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2), - DEF_MOD("rpc-if", 917, R8A77980_CLK_RPC), + DEF_MOD("rpc-if", 917, R8A77980_CLK_RPCD2), DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6), DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6), DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2), |