diff options
| author |   Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2017-04-20 02:46:23 +0900 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2017-05-15 09:46:31 +0200 |
| commit | 66fbee35d51d1cac5bd819e3114b4150de7ec8fb (patch) | |
| tree | 4a1a4e68bcd280731c57b544ffb3997e99ae801e /drivers/clk/renesas | |
| parent | clk: renesas: r8a7745: Remove PLL configs for MD19=0 (diff) | |
| download | linux-dev-66fbee35d51d1cac5bd819e3114b4150de7ec8fb.tar.xz linux-dev-66fbee35d51d1cac5bd819e3114b4150de7ec8fb.zip | |
clk: renesas: r8a7795: Add EHCI/OHCI ch3 clock
This patch supports the clock of EHCI/OHCI ch3 module added from R8A7795
ES2.0 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index eaa98b488f01..3eb8db1868e0 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -189,6 +189,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */ DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1), DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1), + DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4), DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4), DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4), DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), |