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| author |   Heiko Stuebner <heiko@sntech.de> | 2014-11-20 20:38:50 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2014-11-25 09:57:07 +0100 |
| commit | 4f8a7c549f373f33c065c9cbb5a5f3f1a9d8f56c (patch) | |
| tree | 6c3adc9b74f0663ec871a0cc45309b7044657d68 /drivers/clk/rockchip/clk-rk3288.c | |
| parent | clk: rockchip: fix rk3188 USB HSIC PHY clock divider (diff) | |
| download | linux-dev-4f8a7c549f373f33c065c9cbb5a5f3f1a9d8f56c.tar.xz linux-dev-4f8a7c549f373f33c065c9cbb5a5f3f1a9d8f56c.zip | |
clk: rockchip: add ability to specify pll-specific flags
This adds a flag parameter to plls that allows us to create
special flags to tweak the behaviour of the plls if necessary.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3288.c')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3288.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 174589c95e33..2d31a22c0273 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -202,15 +202,15 @@ PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" }; static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0), - RK3288_MODE_CON, 0, 6, rk3288_pll_rates), + RK3288_MODE_CON, 0, 6, 0, rk3288_pll_rates), [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4), - RK3288_MODE_CON, 4, 5, NULL), + RK3288_MODE_CON, 4, 5, 0, NULL), [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8), - RK3288_MODE_CON, 8, 7, rk3288_pll_rates), + RK3288_MODE_CON, 8, 7, 0, rk3288_pll_rates), [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), - RK3288_MODE_CON, 12, 8, rk3288_pll_rates), + RK3288_MODE_CON, 12, 8, 0, rk3288_pll_rates), [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), - RK3288_MODE_CON, 14, 9, rk3288_pll_rates), + RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates), }; static struct clk_div_table div_hclk_cpu_t[] = { |