diff options
| author |   Xing Zheng <zhengxing@rock-chips.com> | 2016-03-09 10:37:03 +0800 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2016-03-27 13:03:33 +0200 |
| commit | 268aebaa2410152bf91ea1ede6b284ff8138822d (patch) | |
| tree | f3831b0a1978eb3eeb0abf22d90e6c839a66f6f0 /drivers/clk/rockchip/clk.h | |
| parent | clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type (diff) | |
| download | linux-dev-268aebaa2410152bf91ea1ede6b284ff8138822d.tar.xz linux-dev-268aebaa2410152bf91ea1ede6b284ff8138822d.zip | |
clk: rockchip: allow varying mux parameters for cpuclk pll-sources
Thers are only two parent PLLs that APLL and GPLL for core on the
previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
GPLL as alternate parent when core is switching freq.
Since RK3399 big.LITTLE architecture, we need to select and adapt
more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk.h')
| -rw-r--r-- | drivers/clk/rockchip/clk.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index f3da205073ee..4133bfc8f827 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -217,14 +217,20 @@ struct rockchip_cpuclk_rate_table { * @core_reg: register offset of the core settings register * @div_core_shift: core divider offset used to divide the pll value * @div_core_mask: core divider mask + * @mux_core_alt: mux value to select alternate parent + * @mux_core_main: mux value to select main parent of core * @mux_core_shift: offset of the core multiplexer + * @mux_core_mask: core multiplexer mask */ struct rockchip_cpuclk_reg_data { int core_reg; u8 div_core_shift; u32 div_core_mask; int mux_core_reg; + u8 mux_core_alt; + u8 mux_core_main; u8 mux_core_shift; + u32 mux_core_mask; }; struct clk *rockchip_clk_register_cpuclk(const char *name, |