diff options
| author |   Tomasz Figa <t.figa@samsung.com> | 2013-08-26 19:09:06 +0200 |
|---|---|---|
| committer |   Mike Turquette <mturquette@linaro.org> | 2013-09-06 13:33:43 -0700 |
| commit | c50d11f35a021fc357922797a7638d4d6ca70b9e (patch) | |
| tree | bdc0c3a42b4cb42e10feee7ae8d11f8fcd93b6d0 /drivers/clk/samsung/clk-exynos4.c | |
| parent | clk: samsung: pll: Add support for rate configuration of PLL45xx (diff) | |
| download | linux-dev-c50d11f35a021fc357922797a7638d4d6ca70b9e.tar.xz linux-dev-c50d11f35a021fc357922797a7638d4d6ca70b9e.zip | |
clk: samsung: pll: Use new registration method for PLL46xx
This patch modifies PLL46xx support code and its users to use the
recently introduced common PLL registration helper.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos4.c')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos4.c | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index fd0215d99c88..779c2069e632 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -985,11 +985,15 @@ static struct of_device_id ext_clk_match[] __initdata = { {}, }; -static struct samsung_pll_clock exynos4210_plls[] __initdata = { +static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = { [apll] = PLL_A(pll_4508, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, "fout_apll", NULL), [mpll] = PLL_A(pll_4508, fout_mpll, "fout_mpll", "fin_pll", E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL), + [epll] = PLL_A(pll_4600, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, + EPLL_CON0, "fout_epll", NULL), + [vpll] = PLL_A(pll_4650c, fout_vpll, "fout_vpll", "mout_vpllsrc", + VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL), }; static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { @@ -1008,8 +1012,6 @@ static void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_soc, void __iomem *reg_base, unsigned long xom) { - struct clk *epll, *vpll; - reg_base = of_iomap(np, 0); if (!reg_base) panic("%s: failed to map registers\n", __func__); @@ -1032,13 +1034,6 @@ static void __init exynos4_clk_init(struct device_node *np, if (exynos4_soc == EXYNOS4210) { samsung_clk_register_pll(exynos4210_plls, ARRAY_SIZE(exynos4210_plls), reg_base); - epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll", - reg_base + EPLL_CON0, pll_4600); - vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc", - reg_base + VPLL_CON0, pll_4650c); - - samsung_clk_add_lookup(epll, fout_epll); - samsung_clk_add_lookup(vpll, fout_vpll); } else { samsung_clk_register_pll(exynos4x12_plls, ARRAY_SIZE(exynos4x12_plls), reg_base); |