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| author |   Alim Akhtar <alim.akhtar@samsung.com> | 2015-08-26 09:00:41 +0530 |
|---|---|---|
| committer |   Sylwester Nawrocki <s.nawrocki@samsung.com> | 2015-09-15 10:58:10 +0200 |
| commit | fa9f3a526459ef33f1ca54aad231c5a23071f37f (patch) | |
| tree | 8bfa7e168b46877b1d4120c57d6ea910fa003262 /drivers/clk/samsung/clk-exynos7.c | |
| parent | Linux 4.3-rc1 (diff) | |
| download | linux-dev-fa9f3a526459ef33f1ca54aad231c5a23071f37f.tar.xz linux-dev-fa9f3a526459ef33f1ca54aad231c5a23071f37f.zip | |
clk: samsung: exynos7: Fix CMU TOPC block clock
Corrects the bit width of DIV_TOPC3 register.
These are wrongly set to 3 which should be 4 bit wide as per UM.
This also adjusts the MUX clock order.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos7.c')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos7.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 8524e667097e..e8cfe9c78866 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -102,9 +102,9 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = { MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p, MUX_SEL_TOPC0, 28, 1), + MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1), MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p, MUX_SEL_TOPC1, 16, 1), - MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1), MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2), @@ -122,15 +122,15 @@ static struct samsung_div_clock topc_div_clks[] __initdata = { DIV_TOPC1, 24, 4), DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out", - DIV_TOPC3, 0, 3), + DIV_TOPC3, 0, 4), DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl", - DIV_TOPC3, 8, 3), + DIV_TOPC3, 8, 4), DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl", - DIV_TOPC3, 12, 3), + DIV_TOPC3, 12, 4), DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl", - DIV_TOPC3, 16, 3), + DIV_TOPC3, 16, 4), DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl", - DIV_TOPC3, 28, 3), + DIV_TOPC3, 28, 4), }; static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = { |