diff options
| author |   Vipul Kumar Samar <vipulkumar.samar@st.com> | 2012-11-10 12:13:43 +0530 |
|---|---|---|
| committer |   Mike Turquette <mturquette@linaro.org> | 2012-11-21 11:45:45 -0800 |
| commit | 1249979242db10d2fe1793f26e7658d94b7bf6dc (patch) | |
| tree | 893efc50099b1ad06e137af84c5cd37f7b33c3b2 /drivers/clk/spear/spear1310_clock.c | |
| parent | CLK: SPEAr13xx: fix parent names of multiple clocks (diff) | |
| download | linux-dev-1249979242db10d2fe1793f26e7658d94b7bf6dc.tar.xz linux-dev-1249979242db10d2fe1793f26e7658d94b7bf6dc.zip | |
CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocks
Flag CLK_SET_RATE_PARENT is required for a clock, where we want to
propagate clk_set_rate to its parent. This patch adds this to multiple clocks.
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Vijay Kumar Mishra <vijay.kumar@st.com>
Signed-off-by: Vijay Kumar Mishra <vijay.kumar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/spear/spear1310_clock.c')
| -rw-r--r-- | drivers/clk/spear/spear1310_clock.c | 49 |
1 files changed, 25 insertions, 24 deletions
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c index e84b1fbb5838..2809b670e22c 100644 --- a/drivers/clk/spear/spear1310_clock.c +++ b/drivers/clk/spear/spear1310_clock.c @@ -483,7 +483,8 @@ void __init spear1310_clk_init(void) clk_register_clkdev(clk, "ddr_clk", NULL); /* clock derived from pll1 clk */ - clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 2); + clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", + CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "cpu_clk", NULL); clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, @@ -547,14 +548,14 @@ void __init spear1310_clk_init(void) clk_register_clkdev(clk1, "uart_syn_gclk", NULL); clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, - ARRAY_SIZE(uart0_parents), 0, SPEAR1310_PERIP_CLK_CFG, - SPEAR1310_UART_CLK_SHIFT, SPEAR1310_UART_CLK_MASK, 0, - &_lock); + ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT, + SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT, + SPEAR1310_UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart0_mclk", NULL); - clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", 0, - SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UART_CLK_ENB, 0, - &_lock); + clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", + CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, + SPEAR1310_UART_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0000000.serial"); clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", @@ -563,9 +564,9 @@ void __init spear1310_clk_init(void) clk_register_clkdev(clk, "sdhci_syn_clk", NULL); clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL); - clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", 0, - SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SDHCI_CLK_ENB, 0, - &_lock); + clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", + CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, + SPEAR1310_SDHCI_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b3000000.sdhci"); clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", @@ -574,9 +575,9 @@ void __init spear1310_clk_init(void) clk_register_clkdev(clk, "cfxd_syn_clk", NULL); clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL); - clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", 0, - SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CFXD_CLK_ENB, 0, - &_lock); + clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", + CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, + SPEAR1310_CFXD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b2800000.cf"); clk_register_clkdev(clk, NULL, "arasan_xd"); @@ -587,9 +588,9 @@ void __init spear1310_clk_init(void) clk_register_clkdev(clk1, "c3_syn_gclk", NULL); clk = clk_register_mux(NULL, "c3_mclk", c3_parents, - ARRAY_SIZE(c3_parents), 0, SPEAR1310_PERIP_CLK_CFG, - SPEAR1310_C3_CLK_SHIFT, SPEAR1310_C3_CLK_MASK, 0, - &_lock); + ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT, + SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT, + SPEAR1310_C3_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "c3_mclk", NULL); clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0, @@ -630,7 +631,7 @@ void __init spear1310_clk_init(void) clk_register_clkdev(clk, "clcd_syn_clk", NULL); clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, - ARRAY_SIZE(clcd_pixel_parents), 0, + ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT, SPEAR1310_CLCD_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); @@ -653,10 +654,10 @@ void __init spear1310_clk_init(void) clk_register_clkdev(clk, "i2s_prs1_clk", NULL); clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, - ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1310_I2S_CLK_CFG, - SPEAR1310_I2S_REF_SHIFT, SPEAR1310_I2S_REF_SEL_MASK, 0, - &_lock); - clk_register_clkdev(clk, "i2s_ref_clk", NULL); + ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT, + SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT, + SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock); + clk_register_clkdev(clk, "i2s_ref_mclk", NULL); clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB, @@ -753,9 +754,9 @@ void __init spear1310_clk_init(void) clk_register_clkdev(clk, "adc_syn_clk", NULL); clk_register_clkdev(clk1, "adc_syn_gclk", NULL); - clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 0, - SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_ADC_CLK_ENB, 0, - &_lock); + clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", + CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, + SPEAR1310_ADC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0080000.adc"); /* clock derived from apb clk */ |