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| author |   Chen-Yu Tsai <wens@csie.org> | 2017-01-28 20:22:33 +0800 |
|---|---|---|
| committer |   Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-01-30 08:36:20 +0100 |
| commit | 3de64bf187ce838b78ccd6ee7c1cc25e0aba07bd (patch) | |
| tree | d8ac6c61d15f902b0a31f3f9e5e86752449ac532 /drivers/clk/sunxi-ng/ccu-sun9i-a80.h | |
| parent | clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT (diff) | |
| download | linux-dev-3de64bf187ce838b78ccd6ee7c1cc25e0aba07bd.tar.xz linux-dev-3de64bf187ce838b78ccd6ee7c1cc25e0aba07bd.zip | |
clk: sunxi-ng: Support separately grouped PLL lock status register
On the Allwinner A80 SoC, the PLL lock status indicators are grouped
together in a separate register, as opposed to being scattered in each
PLL's configuration register.
Add a flag to support this.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu-sun9i-a80.h')
0 files changed, 0 insertions, 0 deletions