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| author |   Chen-Yu Tsai <wens@csie.org> | 2017-12-04 13:19:11 +0800 |
|---|---|---|
| committer |   Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-12-07 10:09:44 +0100 |
| commit | 946797aa3f08e2f6f5992f3ec2be44791e9b9260 (patch) | |
| tree | bf791a74c0914464a21ede67a075fe71dd93cd74 /drivers/clk/sunxi-ng/ccu_mp.h | |
| parent | clk: sunxi: Use PTR_ERR_OR_ZERO() (diff) | |
| download | linux-dev-946797aa3f08e2f6f5992f3ec2be44791e9b9260.tar.xz linux-dev-946797aa3f08e2f6f5992f3ec2be44791e9b9260.zip | |
clk: sunxi-ng: Support fixed post-dividers on MP style clocks
On the A64, the MMC module clocks are fixed in the new timing mode,
i.e. they do not have a bit to select the mode. These clocks have
a 2x divider somewhere between the clock and the MMC module.
To be consistent with other SoCs supporting the new timing mode,
we model the 2x divider as a fixed post-divider on the MMC module
clocks.
To do this, we first add fixed post-divider to the MP style clocks,
which the MMC module clocks are.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu_mp.h')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu_mp.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/clk/sunxi-ng/ccu_mp.h b/drivers/clk/sunxi-ng/ccu_mp.h index aaef11d747ea..5107635e61de 100644 --- a/drivers/clk/sunxi-ng/ccu_mp.h +++ b/drivers/clk/sunxi-ng/ccu_mp.h @@ -33,9 +33,33 @@ struct ccu_mp { struct ccu_div_internal m; struct ccu_div_internal p; struct ccu_mux_internal mux; + + unsigned int fixed_post_div; + struct ccu_common common; }; +#define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ + _mshift, _mwidth, \ + _pshift, _pwidth, \ + _muxshift, _muxwidth, \ + _gate, _postdiv, _flags) \ + struct ccu_mp _struct = { \ + .enable = _gate, \ + .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ + .p = _SUNXI_CCU_DIV(_pshift, _pwidth), \ + .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \ + .fixed_post_div = _postdiv, \ + .common = { \ + .reg = _reg, \ + .features = CCU_FEATURE_FIXED_POSTDIV, \ + .hw.init = CLK_HW_INIT_PARENTS(_name, \ + _parents, \ + &ccu_mp_ops, \ + _flags), \ + } \ + } + #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ _mshift, _mwidth, \ _pshift, _pwidth, \ |