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authorKrzysztof Adamski <k@japko.eu>2016-02-22 14:03:25 +0100
committerMaxime Ripard <maxime.ripard@free-electrons.com>2016-02-25 11:30:32 -0800
commit6e17b4181603d183d20c73f4535529ddf2a2a020 (patch)
treea955d26015816ed7e2d23937fe1e4bb731fd4908 /drivers/clk/sunxi
parentclk: sunxi: Improve divs_clk error handling and reporting (diff)
downloadlinux-dev-6e17b4181603d183d20c73f4535529ddf2a2a020.tar.xz
linux-dev-6e17b4181603d183d20c73f4535529ddf2a2a020.zip
clk: sunxi: Add apb0 gates for H3
This patch adds support for APB0 in H3. It seems to be compatible with earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR, etc). Since this gates behave just like any Allwinner clock gate, add a generic compatible that can be reused if we don't have any clock to protect. Signed-off-by: Krzysztof Adamski <k@japko.eu> [Maxime: Removed the H3 compatible from the simple-gates driver, reworked the commit log a bit] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi')
-rw-r--r--drivers/clk/sunxi/clk-simple-gates.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
index 2cfc5a8a5534..a085c3bc127c 100644
--- a/drivers/clk/sunxi/clk-simple-gates.c
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -98,6 +98,8 @@ static void __init sunxi_simple_gates_init(struct device_node *node)
sunxi_simple_gates_setup(node, NULL, 0);
}
+CLK_OF_DECLARE(sun4i_a10_gates, "allwinner,sun4i-a10-gates-clk",
+ sunxi_simple_gates_init);
CLK_OF_DECLARE(sun4i_a10_apb0, "allwinner,sun4i-a10-apb0-gates-clk",
sunxi_simple_gates_init);
CLK_OF_DECLARE(sun4i_a10_apb1, "allwinner,sun4i-a10-apb1-gates-clk",