diff options
| author |   Wei Yongjun <yongjun_wei@trendmicro.com.cn> | 2016-07-06 12:18:34 +0000 |
|---|---|---|
| committer |   Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-08-08 19:27:33 +0200 |
| commit | 7e196aa1a011da35a04cb1f161e186563aa8d8db (patch) | |
| tree | 548a8c751f01574a023a5aa9e960b31b96a97b9c /drivers/clk/sunxi | |
| parent | Linux 4.8-rc1 (diff) | |
| download | linux-dev-7e196aa1a011da35a04cb1f161e186563aa8d8db.tar.xz linux-dev-7e196aa1a011da35a04cb1f161e186563aa8d8db.zip | |
clk: sunxi: pll2: Fix return value check in sun4i_pll2_setup()
In case of error, the functions clk_register_composite() and
clk_register_divider() returns ERR_PTR() and never returns NULL.
The NULL test in the return value check should be replaced with
IS_ERR().
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi')
| -rw-r--r-- | drivers/clk/sunxi/clk-a10-pll2.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/sunxi/clk-a10-pll2.c b/drivers/clk/sunxi/clk-a10-pll2.c index 0ee1f363e4be..d8eab90ae661 100644 --- a/drivers/clk/sunxi/clk-a10-pll2.c +++ b/drivers/clk/sunxi/clk-a10-pll2.c @@ -73,7 +73,7 @@ static void __init sun4i_pll2_setup(struct device_node *node, SUN4I_PLL2_PRE_DIV_WIDTH, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &sun4i_a10_pll2_lock); - if (!prediv_clk) { + if (IS_ERR(prediv_clk)) { pr_err("Couldn't register the prediv clock\n"); goto err_free_array; } @@ -106,7 +106,7 @@ static void __init sun4i_pll2_setup(struct device_node *node, &mult->hw, &clk_multiplier_ops, &gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT); - if (!base_clk) { + if (IS_ERR(base_clk)) { pr_err("Couldn't register the base multiplier clock\n"); goto err_free_multiplier; } |