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| author |   Russ Dill <Russ.Dill@ti.com> | 2018-09-04 12:19:37 +0530 |
|---|---|---|
| committer |   Tero Kristo <t-kristo@ti.com> | 2018-10-03 15:29:19 +0300 |
| commit | d6e7bbc148f9fbec8a0117b0d0f420c9710e6d81 (patch) | |
| tree | fa2ac59eb7d2afd4b8af48d59dc30d673dd5f2f7 /drivers/clk/ti/dpll.c | |
| parent | clk: clk: Add clk_gate_restore_context function (diff) | |
| download | linux-dev-d6e7bbc148f9fbec8a0117b0d0f420c9710e6d81.tar.xz linux-dev-d6e7bbc148f9fbec8a0117b0d0f420c9710e6d81.zip | |
clk: ti: Add functions to save/restore clk context
SoCs like AM43XX lose clock registers context during RTC-only
suspend. Hence add functions to save/restore the clock registers
context.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'drivers/clk/ti/dpll.c')
| -rw-r--r-- | drivers/clk/ti/dpll.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index dc86d07d0921..25d86d5ebb36 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c @@ -39,6 +39,8 @@ static const struct clk_ops dpll_m4xen_ck_ops = { .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, .determine_rate = &omap4_dpll_regm4xen_determine_rate, .get_parent = &omap2_init_dpll_parent, + .save_context = &omap3_core_dpll_save_context, + .restore_context = &omap3_core_dpll_restore_context, }; #else static const struct clk_ops dpll_m4xen_ck_ops = {}; @@ -62,6 +64,8 @@ static const struct clk_ops dpll_ck_ops = { .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, .determine_rate = &omap3_noncore_dpll_determine_rate, .get_parent = &omap2_init_dpll_parent, + .save_context = &omap3_noncore_dpll_save_context, + .restore_context = &omap3_noncore_dpll_restore_context, }; static const struct clk_ops dpll_no_gate_ck_ops = { @@ -72,6 +76,8 @@ static const struct clk_ops dpll_no_gate_ck_ops = { .set_parent = &omap3_noncore_dpll_set_parent, .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, .determine_rate = &omap3_noncore_dpll_determine_rate, + .save_context = &omap3_noncore_dpll_save_context, + .restore_context = &omap3_noncore_dpll_restore_context }; #else static const struct clk_ops dpll_core_ck_ops = {}; |