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| author |   Mike Turquette <mturquette@linaro.org> | 2013-08-20 14:58:48 -0700 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-08-20 14:58:48 -0700 |
| commit | bddbd13453d838a30baf84869c56076c8ce2b211 (patch) | |
| tree | 024bbb15ed230f23caace4d0178e19c461fb8af8 /drivers/clk/zynq | |
| parent | clk: clk-mux: implement remuxing on set_rate (diff) | |
| parent | clk/zynq/pll: Use #defines for fbdiv min/max values (diff) | |
| download | linux-dev-bddbd13453d838a30baf84869c56076c8ce2b211.tar.xz linux-dev-bddbd13453d838a30baf84869c56076c8ce2b211.zip | |
Merge tag 'zynq-clk-for-3.12' of git://git.xilinx.com/linux-xlnx into clk-next
arm: Xilinx Zynq clock changes for v3.12
Just small two changes where the first fixes
documentation and the second improves
code readability.
Diffstat (limited to 'drivers/clk/zynq')
| -rw-r--r-- | drivers/clk/zynq/pll.c | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c index 47e307c25a7b..3226f54fa595 100644 --- a/drivers/clk/zynq/pll.c +++ b/drivers/clk/zynq/pll.c @@ -50,6 +50,9 @@ struct zynq_pll { #define PLLCTRL_RESET_MASK 1 #define PLLCTRL_RESET_SHIFT 0 +#define PLL_FBDIV_MIN 13 +#define PLL_FBDIV_MAX 66 + /** * zynq_pll_round_rate() - Round a clock frequency * @hw: Handle between common and hardware-specific interfaces @@ -63,10 +66,10 @@ static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate, u32 fbdiv; fbdiv = DIV_ROUND_CLOSEST(rate, *prate); - if (fbdiv < 13) - fbdiv = 13; - else if (fbdiv > 66) - fbdiv = 66; + if (fbdiv < PLL_FBDIV_MIN) + fbdiv = PLL_FBDIV_MIN; + else if (fbdiv > PLL_FBDIV_MAX) + fbdiv = PLL_FBDIV_MAX; return *prate * fbdiv; } @@ -182,7 +185,13 @@ static const struct clk_ops zynq_pll_ops = { /** * clk_register_zynq_pll() - Register PLL with the clock framework - * @np Pointer to the DT device node + * @name PLL name + * @parent Parent clock name + * @pll_ctrl Pointer to PLL control register + * @pll_status Pointer to PLL status register + * @lock_index Bit index to this PLL's lock status bit in @pll_status + * @lock Register lock + * Returns handle to the registered clock. */ struct clk *clk_register_zynq_pll(const char *name, const char *parent, void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index, |