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| author |   Peter De Schrijver <pdeschrijver@nvidia.com> | 2017-07-25 13:34:03 +0300 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@codeaurora.org> | 2017-08-23 15:57:06 -0700 |
| commit | 04434cfa2b2032eae52c197ea184844dd76a329d (patch) | |
| tree | 3f7263efc0a64db1da37019b1e76288bc09858ed /drivers/clk | |
| parent | clk: tegra: fix SS control on PLL enable/disable (diff) | |
| download | linux-dev-04434cfa2b2032eae52c197ea184844dd76a329d.tar.xz linux-dev-04434cfa2b2032eae52c197ea184844dd76a329d.zip | |
clk: tegra: Enable PLL_SS for Tegra210
Make sure the pll_ss ops are compiled even when only building for Tegra210.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/tegra/clk-pll.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index e9bdb1662219..fbd8726213ab 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -2255,7 +2255,7 @@ tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name, } #endif -#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) +#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) || defined(CONFIG_ARCH_TEGRA_210_SOC) static const struct clk_ops tegra_clk_pllss_ops = { .is_enabled = clk_pll_is_enabled, .enable = clk_pll_enable, |