diff options
| author |   Rajan Vaja <rajan.vaja@xilinx.com> | 2021-06-28 00:01:20 -0700 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2021-06-28 23:35:36 -0700 |
| commit | 1b09c308e64969f545f4b9474b786ad90dddf9a2 (patch) | |
| tree | 885f6600e8a6bbe32f67f386d862fd0f9e4cb6bb /drivers/clk | |
| parent | clk: zynqmp: Use firmware specific common clock flags (diff) | |
| download | linux-dev-1b09c308e64969f545f4b9474b786ad90dddf9a2.tar.xz linux-dev-1b09c308e64969f545f4b9474b786ad90dddf9a2.zip | |
clk: zynqmp: Use firmware specific divider clock flags
Use ZynqMP specific divider clock flags instead of using CCF flags.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Link: https://lore.kernel.org/r/20210628070122.26217-3-rajan.vaja@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/zynqmp/clk-zynqmp.h | 9 | ||||
| -rw-r--r-- | drivers/clk/zynqmp/divider.c | 25 |
2 files changed, 33 insertions, 1 deletions
diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h index aa013a59c7cc..925a727eb383 100644 --- a/drivers/clk/zynqmp/clk-zynqmp.h +++ b/drivers/clk/zynqmp/clk-zynqmp.h @@ -24,6 +24,15 @@ /* do not gate, ever */ #define ZYNQMP_CLK_IS_CRITICAL BIT(11) +/* Type Flags for divider clock */ +#define ZYNQMP_CLK_DIVIDER_ONE_BASED BIT(0) +#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO BIT(1) +#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK BIT(3) +#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST BIT(4) +#define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5) +#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6) + enum topology_type { TYPE_INVALID, TYPE_MUX, diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 0becdc0a8bff..c07423e03bc8 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -284,6 +284,29 @@ static u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type) return ret_payload[1]; } +static inline unsigned long zynqmp_clk_map_divider_ccf_flags( + const u32 zynqmp_type_flag) +{ + unsigned long ccf_flag = 0; + + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ONE_BASED) + ccf_flag |= CLK_DIVIDER_ONE_BASED; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) + ccf_flag |= CLK_DIVIDER_POWER_OF_TWO; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ALLOW_ZERO) + ccf_flag |= CLK_DIVIDER_ALLOW_ZERO; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) + ccf_flag |= CLK_DIVIDER_HIWORD_MASK; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST) + ccf_flag |= CLK_DIVIDER_ROUND_CLOSEST; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_READ_ONLY) + ccf_flag |= CLK_DIVIDER_READ_ONLY; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO) + ccf_flag |= CLK_DIVIDER_MAX_AT_ZERO; + + return ccf_flag; +} + /** * zynqmp_clk_register_divider() - Register a divider clock * @name: Name of this clock @@ -321,7 +344,7 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name, /* struct clk_divider assignments */ div->is_frac = !!((nodes->flag & CLK_FRAC) | (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC)); - div->flags = nodes->type_flag; + div->flags = zynqmp_clk_map_divider_ccf_flags(nodes->type_flag); div->hw.init = &init; div->clk_id = clk_id; div->div_type = nodes->type; |