diff options
| author |   Dmitry Osipenko <digetx@gmail.com> | 2019-12-18 21:44:07 +0300 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2020-01-10 15:50:43 +0100 |
| commit | 41a1f096e94c9559b45ccce43fba94913ebc7313 (patch) | |
| tree | 9d6a2c3deaacaa233bff4dbce8506ebcb8f5f74f /drivers/clk | |
| parent | clk: tegra20/30: Don't pre-initialize displays parent clock (diff) | |
| download | linux-dev-41a1f096e94c9559b45ccce43fba94913ebc7313.tar.xz linux-dev-41a1f096e94c9559b45ccce43fba94913ebc7313.zip | |
clk: tegra20/30: Explicitly set parent clock for Video Decoder
The VDE parent won't be changed automatically to PLLC if bootloader
didn't do that for us, hence let's explicitly set the parent for
consistency.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra20.c | 2 | ||||
| -rw-r--r-- | drivers/clk/tegra/clk-tegra30.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 0c14fb570343..fff5cba87637 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1048,7 +1048,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 }, { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 }, { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, - { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 }, + { TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 }, /* must be the last entry */ { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, }; diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index bd4d42005897..b20891489e11 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1256,7 +1256,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 }, - { TEGRA30_CLK_VDE, TEGRA30_CLK_CLK_MAX, 600000000, 0 }, + { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 600000000, 0 }, { TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, |