diff options
| author |   Jon Hunter <jonathanh@nvidia.com> | 2015-12-18 13:45:28 +0000 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2016-02-02 15:49:30 +0100 |
| commit | 4f8d44403079991a29e69f6aa25bb718ead418cb (patch) | |
| tree | 48713f62eead2fd1be115b342c46cd85076300c1 /drivers/clk | |
| parent | clk: tegra: Add the APB2APE audio clock on Tegra210 (diff) | |
| download | linux-dev-4f8d44403079991a29e69f6aa25bb718ead418cb.tar.xz linux-dev-4f8d44403079991a29e69f6aa25bb718ead418cb.zip | |
clk: tegra: Fix clock sources for Tegra210 EMC
The EMC clock sources for Tegra210 currently incorrectly include pll_c2
and pll_c3. However, both of these should have been pll_mb as shown in
the TRM. If Tegra210 happens to be configured such that the pll_mb is the
default clock for the EMC, as configured by the bootloader, then this will
cause a system hang on boot. This is because the kernel will disable the
pll_mb when disabling unused clock as it appears to be unused when it is
not.
Also add the additional pll_p clock source for the EMC.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra210.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 14c1841eb29b..429eec96696e 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -243,7 +243,8 @@ static unsigned long tegra210_input_freq[] = { }; static const char *mux_pllmcp_clkm[] = { - "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3", + "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb", + "pll_p", }; #define mux_pllmcp_clkm_idx NULL |