diff options
| author |   Michał Mirosław <mirq-linux@rere.qmqm.pl> | 2017-09-19 04:48:10 +0200 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2017-11-01 15:00:06 +0100 |
| commit | 54eff2264d3e9fd7e3987de1d7eba1d3581c631e (patch) | |
| tree | efc64cd2a02c839a6fb1a657da81ab76ec7cfdf2 /drivers/clk | |
| parent | clk: tegra: Bump SCLK clock rate to 216 MHz (diff) | |
| download | linux-dev-54eff2264d3e9fd7e3987de1d7eba1d3581c631e.tar.xz linux-dev-54eff2264d3e9fd7e3987de1d7eba1d3581c631e.zip | |
clk: tegra: Fix cclk_lp divisor register
According to comments in code and common sense, cclk_lp uses its
own divisor, not cclk_g's.
Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30")
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra30.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 40ffab0f94e1..bee84c554932 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -965,7 +965,7 @@ static void __init tegra30_super_clk_init(void) * U71 divider of cclk_lp. */ clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3", - clk_base + SUPER_CCLKG_DIVIDER, 0, + clk_base + SUPER_CCLKLP_DIVIDER, 0, TEGRA_DIVIDER_INT, 16, 8, 1, NULL); clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL); |