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| author |   Pankaj Dev <pankaj.dev@st.com> | 2015-07-07 09:40:50 +0200 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@codeaurora.org> | 2015-07-07 16:05:08 -0700 |
| commit | 56551da9255f20ffd3a9711728a1a3ad4b7100af (patch) | |
| tree | fb5ca1d7286bb74a5789f273fbc7ee23895e47d8 /drivers/clk | |
| parent | clk: mediatek: mt8173: Fix enabling of critical clocks (diff) | |
| download | linux-dev-56551da9255f20ffd3a9711728a1a3ad4b7100af.tar.xz linux-dev-56551da9255f20ffd3a9711728a1a3ad4b7100af.zip | |
drivers: clk: st: Incorrect register offset used for lock_status
Incorrect register offset used for sthi407 clockgenC
Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Fixes: 51306d56ba81 ("clk: st: STiH407: Support for clockgenC0")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/st/clkgen-fsyn.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c index 99c98c15d4a4..d9eb2e1d8471 100644 --- a/drivers/clk/st/clkgen-fsyn.c +++ b/drivers/clk/st/clkgen-fsyn.c @@ -340,7 +340,7 @@ static const struct clkgen_quadfs_data st_fs660c32_C_407 = { CLKGEN_FIELD(0x30c, 0xf, 20), CLKGEN_FIELD(0x310, 0xf, 20) }, .lockstatus_present = true, - .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24), + .lock_status = CLKGEN_FIELD(0x2f0, 0x1, 24), .powerup_polarity = 1, .standby_polarity = 1, .pll_ops = &st_quadfs_pll_c32_ops, |