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| author |   Hanks Chen <hanks.chen@mediatek.com> | 2020-07-30 21:30:16 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2020-10-08 14:45:16 -0700 |
| commit | 804a892456b73604b7ecfb1b00a96a29f3d2aedf (patch) | |
| tree | 9c6188449a40ded2933f726ba2e021b78f287fe0 /drivers/clk | |
| parent | Linux 5.9-rc1 (diff) | |
| download | linux-dev-804a892456b73604b7ecfb1b00a96a29f3d2aedf.tar.xz linux-dev-804a892456b73604b7ecfb1b00a96a29f3d2aedf.zip | |
clk: mediatek: add UART0 clock support
Add MT6779 UART0 clock support.
Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
Signed-off-by: Wendell Lin <wendell.lin@mediatek.com>
Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/mediatek/clk-mt6779.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 9766cccf5844..6e0d3a166729 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = { "pwm_sel", 19), GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21), + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", + "uart_sel", 22), GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", |