diff options
| author |   Jacky Bai <ping.bai@nxp.com> | 2019-04-25 08:10:08 +0000 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2019-04-29 16:02:01 -0700 |
| commit | 8cd117e712e17bc9af07638d73261603ef8f4e8d (patch) | |
| tree | 657487d5fece702df93cf2b7d4c89f70ba09d9cd /drivers/clk | |
| parent | clk: imx: correct i.MX7D AV PLL num/denom offset (diff) | |
| download | linux-dev-8cd117e712e17bc9af07638d73261603ef8f4e8d.tar.xz linux-dev-8cd117e712e17bc9af07638d73261603ef8f4e8d.zip | |
clk: imx: keep uart clock on during system boot
Keep uart clocks enabled when earlyprintk or
earlycon is active.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/imx/clk-imx6sll.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx6sll.c b/drivers/clk/imx/clk-imx6sll.c index 9def76df0879..7eea448cb9a9 100644 --- a/drivers/clk/imx/clk-imx6sll.c +++ b/drivers/clk/imx/clk-imx6sll.c @@ -76,6 +76,20 @@ static u32 share_count_ssi1; static u32 share_count_ssi2; static u32 share_count_ssi3; +static struct clk ** const uart_clks[] __initconst = { + &clks[IMX6SLL_CLK_UART1_IPG], + &clks[IMX6SLL_CLK_UART1_SERIAL], + &clks[IMX6SLL_CLK_UART2_IPG], + &clks[IMX6SLL_CLK_UART2_SERIAL], + &clks[IMX6SLL_CLK_UART3_IPG], + &clks[IMX6SLL_CLK_UART3_SERIAL], + &clks[IMX6SLL_CLK_UART4_IPG], + &clks[IMX6SLL_CLK_UART4_SERIAL], + &clks[IMX6SLL_CLK_UART5_IPG], + &clks[IMX6SLL_CLK_UART5_SERIAL], + NULL +}; + static void __init imx6sll_clocks_init(struct device_node *ccm_node) { struct device_node *np; @@ -334,6 +348,8 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node) clk_data.clk_num = ARRAY_SIZE(clks); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + imx_register_uart_clocks(uart_clks); + /* Lower the AHB clock rate before changing the clock source. */ clk_set_rate(clks[IMX6SLL_CLK_AHB], 99000000); |