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| author |   Icenowy Zheng <icenowy@aosc.io> | 2017-07-23 18:27:45 +0800 |
|---|---|---|
| committer |   Chen-Yu Tsai <wens@csie.org> | 2017-08-04 12:05:33 +0800 |
| commit | 913c3d85b4b562e38242765baa95113c8c7f1c14 (patch) | |
| tree | 1a0d0326366d15eb0bd06b8ba60de24ea4277f2c /drivers/clk | |
| parent | clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change (diff) | |
| download | linux-dev-913c3d85b4b562e38242765baa95113c8c7f1c14.tar.xz linux-dev-913c3d85b4b562e38242765baa95113c8c7f1c14.zip | |
clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
can be adjusted by changing the frequency of the PLL_CPUX clock.
Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
clock can be adjusted when adjusting the CPUX clock.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c index 406d0aac9fd6..4cdbc88f2783 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c @@ -135,7 +135,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", static const char * const cpux_parents[] = { "osc32k", "osc24M", "pll-cpux" , "pll-cpux" }; static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, - 0x050, 16, 2, CLK_IS_CRITICAL); + 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT); static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0); |