diff options
| author |   ABE Hiroshige <hiroshige.abe.zc@renesas.com> | 2017-12-14 22:50:55 +0900 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2018-01-05 11:14:38 +0100 |
| commit | a115f6362cee01813c66e10e397b25f2a06aecfb (patch) | |
| tree | 45a53ba7c8c15393cd1d2e9e2a93251f8e7f248e /drivers/clk | |
| parent | clk: renesas: cpg-mssr: Keep wakeup sources active during system suspend (diff) | |
| download | linux-dev-a115f6362cee01813c66e10e397b25f2a06aecfb.tar.xz linux-dev-a115f6362cee01813c66e10e397b25f2a06aecfb.zip | |
clk: renesas: r8a7796: Add FDP clock
This patch adds FDP1-0 clock to the R8A7796 SoC.
Signed-off-by: ABE Hiroshige <hiroshige.abe.zc@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: s/fdp0/fdp1-0/]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index b3767472088a..41e29734126b 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -115,6 +115,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { + DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1), DEF_MOD("scif5", 202, R8A7796_CLK_S3D4), DEF_MOD("scif4", 203, R8A7796_CLK_S3D4), DEF_MOD("scif3", 204, R8A7796_CLK_S3D4), |