diff options
| author |   Sowjanya Komatineni <skomatineni@nvidia.com> | 2019-08-16 12:41:48 -0700 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2019-11-11 14:53:01 +0100 |
| commit | d64422d93dca8fb630a132b0c24680c82c51788b (patch) | |
| tree | 9c9329d84aca84da8ac61e8c8dc445ee84a1dab9 /drivers/clk | |
| parent | clk: tegra: Reimplement SOR clocks on Tegra210 (diff) | |
| download | linux-dev-d64422d93dca8fb630a132b0c24680c82c51788b.tar.xz linux-dev-d64422d93dca8fb630a132b0c24680c82c51788b.zip | |
clk: tegra: divider: Save and restore divider rate
This patch implements context restore for clock divider.
During system suspend, core power goes off and looses the settings
of the Tegra CAR controller registers.
So on resume, clock dividers are restored back for normal operation.
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/tegra/clk-divider.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index e76731fb7d69..ca0de5f11f84 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -109,10 +109,21 @@ static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static void clk_divider_restore_context(struct clk_hw *hw) +{ + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + unsigned long rate = clk_hw_get_rate(hw); + + if (clk_frac_div_set_rate(hw, rate, parent_rate) < 0) + WARN_ON(1); +} + const struct clk_ops tegra_clk_frac_div_ops = { .recalc_rate = clk_frac_div_recalc_rate, .set_rate = clk_frac_div_set_rate, .round_rate = clk_frac_div_round_rate, + .restore_context = clk_divider_restore_context, }; struct clk *tegra_clk_register_divider(const char *name, |