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| author |   Stephen Boyd <sboyd@kernel.org> | 2018-08-14 22:58:39 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-08-14 22:58:39 -0700 |
| commit | ea4f7872c71adef8897f71bb6bb056856ccc8ed9 (patch) | |
| tree | 61658737767f6f7ca4830b2bc2f8126a061e7458 /drivers/clk | |
| parent | Merge branches 'clk-imx6-video-parent', 'clk-qcom-sdm845-criticals', 'clk-renesas', 'clk-stratix10-fixes' and 'clk-atmel-i2s' into clk-next (diff) | |
| parent | clk: ingenic: Add missing flag for UDC clock (diff) | |
| parent | clk: Add driver for MAX9485 (diff) | |
| parent | clk: pxa: export 32kHz PLL (diff) | |
| parent | clk: aspeed: Fix SDCLK name (diff) | |
| parent | clk: imx6sll: add GPIO LPCGs (diff) | |
| download | linux-dev-ea4f7872c71adef8897f71bb6bb056856ccc8ed9.tar.xz linux-dev-ea4f7872c71adef8897f71bb6bb056856ccc8ed9.zip | |
Merge branches 'clk-ingenic-fixes', 'clk-max9485', 'clk-pxa-32k-pll', 'clk-aspeed' and 'clk-imx6sll-gpio' into clk-next
* clk-ingenic-fixes:
: - Ingenic i2s bit update and allow UDC clk to gate
clk: ingenic: Add missing flag for UDC clock
clk: ingenic: Fix incorrect data for the i2s clock
* clk-max9485:
: - Maxim 9485 Programmable Clock Generator
clk: Add driver for MAX9485
dts: clk: add devicetree bindings for MAX9485
* clk-pxa-32k-pll:
: - Expose 32 kHz PLL on PXA SoCs
clk: pxa: export 32kHz PLL
* clk-aspeed:
: - Fix name of aspeed SDC clk define to have only one 'CLK'
clk: aspeed: Fix SDCLK name
* clk-imx6sll-gpio:
: - imx6sll GPIO clk gate support
clk: imx6sll: add GPIO LPCGs