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| author |   Kunkun Jiang <jiangkunkun@huawei.com> | 2022-09-14 14:14:24 +0800 |
|---|---|---|
| committer |   Daniel Lezcano <daniel.lezcano@linaro.org> | 2022-09-20 10:49:45 +0200 |
| commit | 6c3b62d93e195f78c1437c8fa7581e9b2f00886e (patch) | |
| tree | f43cf1651a09e9ec5c8ac9676193fa0ad388b23e /drivers/clocksource/arm_arch_timer.c | |
| parent | clocksource/drivers/exynos_mct: Enable building on ARTPEC (diff) | |
| download | linux-dev-6c3b62d93e195f78c1437c8fa7581e9b2f00886e.tar.xz linux-dev-6c3b62d93e195f78c1437c8fa7581e9b2f00886e.zip | |
clocksource/drivers/arm_arch_timer: Fix handling of ARM erratum 858921
The commit a38b71b0833e ("clocksource/drivers/arm_arch_timer:
Move system register timer programming over to CVAL") moves the
programming of the timers from the countdown timer (TVAL) over
to the comparator (CVAL). This makes it necessary to read the
counter when programming next event. However, the workaround of
Cortex-A73 erratum 858921 does not set the corresponding
set_next_event_phys and set_next_event_virt.
Add the appropriate hooks to apply the erratum mitigation when
programming the next timer event.
Fixes: a38b71b0833e ("clocksource/drivers/arm_arch_timer: Move system register timer programming over to CVAL")
Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20220914061424.1260-1-jiangkunkun@huawei.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'drivers/clocksource/arm_arch_timer.c')
| -rw-r--r-- | drivers/clocksource/arm_arch_timer.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 9ab8221ee3c6..ff935efb6a88 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -473,6 +473,8 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { .desc = "ARM erratum 858921", .read_cntpct_el0 = arm64_858921_read_cntpct_el0, .read_cntvct_el0 = arm64_858921_read_cntvct_el0, + .set_next_event_phys = erratum_set_next_event_phys, + .set_next_event_virt = erratum_set_next_event_virt, }, #endif #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1 |