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| author |   Palmer Dabbelt <palmer@sifive.com> | 2018-10-02 12:14:59 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-10-22 17:03:36 -0700 |
| commit | 9639a44394b9859a5576cb36630105733a552bd6 (patch) | |
| tree | 6e4ad36c54561c3efa773e06aaaf636eed0fc3b6 /drivers/clocksource/riscv_timer.c | |
| parent | RISC-V: Disable preemption before enabling interrupts (diff) | |
| download | linux-dev-9639a44394b9859a5576cb36630105733a552bd6.tar.xz linux-dev-9639a44394b9859a5576cb36630105733a552bd6.zip | |
RISC-V: Provide a cleaner raw_smp_processor_id()
I'm not sure how I managed to miss this the first time, but this is much
better.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
[Atish: code comment formatting and other fixes]
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'drivers/clocksource/riscv_timer.c')
0 files changed, 0 insertions, 0 deletions