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| author |   Christoph Hellwig <hch@lst.de> | 2019-08-21 23:58:36 +0900 |
|---|---|---|
| committer |   Paul Walmsley <paul.walmsley@sifive.com> | 2019-09-05 01:52:46 -0700 |
| commit | 2f12dbf190d97dc0f2f8a07269dd0d8060808539 (patch) | |
| tree | d699e8fc51c7814904c0ab79c50a7144e243d544 /drivers/clocksource/timer-riscv.c | |
| parent | riscv: cleanup riscv_cpuid_to_hartid_mask (diff) | |
| download | linux-dev-2f12dbf190d97dc0f2f8a07269dd0d8060808539.tar.xz linux-dev-2f12dbf190d97dc0f2f8a07269dd0d8060808539.zip | |
riscv: don't use the rdtime(h) pseudo-instructions
If we just use the CSRs that these map to directly the code is simpler
and doesn't require extra inline assembly code. Also fix up the top-level
comment in timer-riscv.c to not talk about the cycle count or mention
details of the clocksource interface, of which this file is just a
consumer.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'drivers/clocksource/timer-riscv.c')
| -rw-r--r-- | drivers/clocksource/timer-riscv.c | 17 |
1 files changed, 4 insertions, 13 deletions
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 09e031176bc6..470c7ef02ea4 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -2,6 +2,10 @@ /* * Copyright (C) 2012 Regents of the University of California * Copyright (C) 2017 SiFive + * + * All RISC-V systems have a timer attached to every hart. These timers can be + * read from the "time" and "timeh" CSRs, and can use the SBI to setup + * events. */ #include <linux/clocksource.h> #include <linux/clockchips.h> @@ -12,19 +16,6 @@ #include <asm/smp.h> #include <asm/sbi.h> -/* - * All RISC-V systems have a timer attached to every hart. These timers can be - * read by the 'rdcycle' pseudo instruction, and can use the SBI to setup - * events. In order to abstract the architecture-specific timer reading and - * setting functions away from the clock event insertion code, we provide - * function pointers to the clockevent subsystem that perform two basic - * operations: rdtime() reads the timer on the current CPU, and - * next_event(delta) sets the next timer event to 'delta' cycles in the future. - * As the timers are inherently a per-cpu resource, these callbacks perform - * operations on the current hart. There is guaranteed to be exactly one timer - * per hart on all RISC-V systems. - */ - static int riscv_clock_next_event(unsigned long delta, struct clock_event_device *ce) { |