diff options
| author |   William Breathitt Gray <vilhelm.gray@gmail.com> | 2021-08-27 12:47:45 +0900 |
|---|---|---|
| committer |   Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2021-10-17 10:52:29 +0100 |
| commit | 05593a3fd1037b5fee85d3c8c28112f19e7baa06 (patch) | |
| tree | 30eca0b5e8fc8de252fa783f8a16d32894ea3a7d /drivers/counter/stm32-lptimer-cnt.c | |
| parent | Linux 5.15-rc1 (diff) | |
| download | linux-dev-05593a3fd1037b5fee85d3c8c28112f19e7baa06.tar.xz linux-dev-05593a3fd1037b5fee85d3c8c28112f19e7baa06.zip | |
counter: stm32-lptimer-cnt: Provide defines for clock polarities
The STM32 low-power timer permits configuration of the clock polarity
via the LPTIMX_CFGR register CKPOL bits. This patch provides
preprocessor defines for the supported clock polarities.
Cc: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/a111c8905c467805ca530728f88189b59430f27e.1630031207.git.vilhelm.gray@gmail.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'drivers/counter/stm32-lptimer-cnt.c')
| -rw-r--r-- | drivers/counter/stm32-lptimer-cnt.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/counter/stm32-lptimer-cnt.c b/drivers/counter/stm32-lptimer-cnt.c index 13656957c45f..7367f46c6f91 100644 --- a/drivers/counter/stm32-lptimer-cnt.c +++ b/drivers/counter/stm32-lptimer-cnt.c @@ -140,9 +140,9 @@ static const enum counter_function stm32_lptim_cnt_functions[] = { }; enum stm32_lptim_synapse_action { - STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE, - STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE, - STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES, + STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE = STM32_LPTIM_CKPOL_RISING_EDGE, + STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE = STM32_LPTIM_CKPOL_FALLING_EDGE, + STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES = STM32_LPTIM_CKPOL_BOTH_EDGES, STM32_LPTIM_SYNAPSE_ACTION_NONE, }; |