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| author |   Ahmad Fatoum <a.fatoum@pengutronix.de> | 2022-05-13 16:57:01 +0200 |
|---|---|---|
| committer |   Jarkko Sakkinen <jarkko@kernel.org> | 2022-05-23 18:47:50 +0300 |
| commit | 7a0e7d5265f58eab5983f6560817d4fe9943743b (patch) | |
| tree | ffea767113f5ac62367d676fc752fd0ecc7f5d5f /drivers/crypto/caam/regs.h | |
| parent | KEYS: trusted: allow use of kernel RNG for key material (diff) | |
| download | linux-dev-7a0e7d5265f58eab5983f6560817d4fe9943743b.tar.xz linux-dev-7a0e7d5265f58eab5983f6560817d4fe9943743b.zip | |
crypto: caam - determine whether CAAM supports blob encap/decap
Depending on SoC variant, a CAAM may be available, but with some futures
fused out. The LS1028A (non-E) SoC is one such SoC and while it
indicates BLOB support, BLOB operations will ultimately fail, because
there is no AES support. Add a new blob_present member to reflect
whether both BLOB support and the AES support it depends on is
available.
These will be used in a follow-up commit to allow blob driver
initialization to error out on SoCs without the necessary hardware
support instead of failing at runtime with a cryptic
caam_jr 8020000.jr: 20000b0f: CCB: desc idx 11: : Invalid CHA selected.
Co-developed-by: Michael Walle <michael@walle.cc>
Signed-off-by: Michael Walle <michael@walle.cc>
Tested-by: Michael Walle <michael@walle.cc> # on ls1028a (non-E and E)
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jarkko Sakkinen <jarkko@kernel.org>
Diffstat (limited to 'drivers/crypto/caam/regs.h')
| -rw-r--r-- | drivers/crypto/caam/regs.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h index 3738625c0250..66d6dad841bb 100644 --- a/drivers/crypto/caam/regs.h +++ b/drivers/crypto/caam/regs.h @@ -320,7 +320,8 @@ struct version_regs { #define CHA_VER_VID_MASK (0xffull << CHA_VER_VID_SHIFT) /* CHA Miscellaneous Information - AESA_MISC specific */ -#define CHA_VER_MISC_AES_GCM BIT(1 + CHA_VER_MISC_SHIFT) +#define CHA_VER_MISC_AES_NUM_MASK GENMASK(7, 0) +#define CHA_VER_MISC_AES_GCM BIT(1 + CHA_VER_MISC_SHIFT) /* CHA Miscellaneous Information - PKHA_MISC specific */ #define CHA_VER_MISC_PKHA_NO_CRYPT BIT(7 + CHA_VER_MISC_SHIFT) @@ -414,6 +415,7 @@ struct caam_perfmon { #define CTPR_MS_PG_SZ_MASK 0x10 #define CTPR_MS_PG_SZ_SHIFT 4 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */ +#define CTPR_LS_BLOB BIT(1) u32 comp_parms_ls; /* CTPR - Compile Parameters Register */ u64 rsvd1[2]; |