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| author |   Harsh Jain <harsh@chelsio.com> | 2017-06-15 12:43:43 +0530 |
|---|---|---|
| committer |   Herbert Xu <herbert@gondor.apana.org.au> | 2017-06-20 11:21:35 +0800 |
| commit | b8fd1f4170e7e8bda45d7bcc750e909c859ec714 (patch) | |
| tree | ed3805bce0ae00492bc44acafea3f3fa24516584 /drivers/crypto/chelsio/chcr_core.h | |
| parent | crypto: chcr - Avoid changing request structure (diff) | |
| download | linux-dev-b8fd1f4170e7e8bda45d7bcc750e909c859ec714.tar.xz linux-dev-b8fd1f4170e7e8bda45d7bcc750e909c859ec714.zip | |
crypto: chcr - Add ctr mode and process large sg entries for cipher
It send multiple WRs to H/W to handle large sg lists. Adds ctr(aes)
and rfc(ctr(aes)) modes.
Signed-off-by: Harsh Jain <harsh@chelsio.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/chelsio/chcr_core.h')
| -rw-r--r-- | drivers/crypto/chelsio/chcr_core.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/crypto/chelsio/chcr_core.h b/drivers/crypto/chelsio/chcr_core.h index cd0c35a18d92..ddfb2c934551 100644 --- a/drivers/crypto/chelsio/chcr_core.h +++ b/drivers/crypto/chelsio/chcr_core.h @@ -53,6 +53,9 @@ #define MAC_ERROR_BIT 0 #define CHK_MAC_ERR_BIT(x) (((x) >> MAC_ERROR_BIT) & 1) #define MAX_SALT 4 +#define WR_MIN_LEN (sizeof(struct chcr_wr) + \ + sizeof(struct cpl_rx_phys_dsgl) + \ + sizeof(struct ulptx_sgl)) #define padap(dev) pci_get_drvdata(dev->u_ctx->lldi.pdev) |