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| author |   Dan Williams <dan.j.williams@intel.com> | 2022-05-18 16:34:48 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-05-19 08:50:41 -0700 |
| commit | 14d78874077442d1d0f08129f5a0ea5070984b4b (patch) | |
| tree | 4c80ac1f7f8fb934b3a430fdcdacee9d40e47f05 /drivers/cxl/cxlpci.h | |
| parent | cxl/pci: Move cxl_await_media_ready() to the core (diff) | |
| download | linux-dev-14d78874077442d1d0f08129f5a0ea5070984b4b.tar.xz linux-dev-14d78874077442d1d0f08129f5a0ea5070984b4b.zip | |
cxl/mem: Consolidate CXL DVSEC Range enumeration in the core
In preparation for fixing the setting of the 'mem_enabled' bit in CXL
DVSEC Control register, move all CXL DVSEC range enumeration into the
same source file.
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165291688886.1426646.15046138604010482084.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/cxlpci.h')
| -rw-r--r-- | drivers/cxl/cxlpci.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 329e7ea3f36a..ad1b62843195 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -72,4 +72,8 @@ static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev, } int devm_cxl_port_enumerate_dports(struct cxl_port *port); +struct cxl_dev_state; +struct cxl_endpoint_dvsec_info; +int cxl_dvsec_ranges(struct cxl_dev_state *cxlds, + struct cxl_endpoint_dvsec_info *info); #endif /* __CXL_PCI_H__ */ |