diff options
| author |   Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2016-08-17 19:20:20 +0300 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-08-31 16:13:29 +0200 |
| commit | 9217a5bf66061c392e461255c5d9d41aac136e58 (patch) | |
| tree | ec3489f8a1c47a108fe956e56b37c27048746c21 /drivers/dma/dw | |
| parent | sc16is7xx: make sure device is in suspend once probed (diff) | |
| download | linux-dev-9217a5bf66061c392e461255c5d9d41aac136e58.tar.xz linux-dev-9217a5bf66061c392e461255c5d9d41aac136e58.zip | |
dmaengine: dw: keep copy of custom slave config in dwc
It seems we need to extend custom slave configuration by one more member to
support Intel Quart UART. It becomes a burden to manage all members of struct
dw_dma_slave one-by-one.
Replace the set of fields by embedding struct dw_dma_slave into struct
dw_dma_chan.
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/dma/dw')
| -rw-r--r-- | drivers/dma/dw/core.c | 29 | ||||
| -rw-r--r-- | drivers/dma/dw/regs.h | 5 |
2 files changed, 11 insertions, 23 deletions
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index edf053f73a49..81b06dfd7e06 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -46,9 +46,9 @@ u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ DW_DMA_MSIZE_16; \ u8 _dms = (_dwc->direction == DMA_MEM_TO_DEV) ? \ - _dwc->p_master : _dwc->m_master; \ + _dwc->dws.p_master : _dwc->dws.m_master; \ u8 _sms = (_dwc->direction == DMA_DEV_TO_MEM) ? \ - _dwc->p_master : _dwc->m_master; \ + _dwc->dws.p_master : _dwc->dws.m_master; \ \ (DWC_CTLL_DST_MSIZE(_dmsize) \ | DWC_CTLL_SRC_MSIZE(_smsize) \ @@ -147,8 +147,8 @@ static void dwc_initialize(struct dw_dma_chan *dwc) if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags)) return; - cfghi |= DWC_CFGH_DST_PER(dwc->dst_id); - cfghi |= DWC_CFGH_SRC_PER(dwc->src_id); + cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id); + cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id); channel_writel(dwc, CFG_LO, cfglo); channel_writel(dwc, CFG_HI, cfghi); @@ -209,7 +209,7 @@ static inline void dwc_do_single_block(struct dw_dma_chan *dwc, static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) { struct dw_dma *dw = to_dw_dma(dwc->chan.device); - u8 lms = DWC_LLP_LMS(dwc->m_master); + u8 lms = DWC_LLP_LMS(dwc->dws.m_master); unsigned long was_soft_llp; /* ASSERT: channel is idle */ @@ -662,7 +662,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, struct dw_desc *prev; size_t xfer_count; size_t offset; - u8 m_master = dwc->m_master; + u8 m_master = dwc->dws.m_master; unsigned int src_width; unsigned int dst_width; unsigned int data_width = dw->pdata->data_width[m_master]; @@ -740,7 +740,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, struct dw_desc *prev; struct dw_desc *first; u32 ctllo; - u8 m_master = dwc->m_master; + u8 m_master = dwc->dws.m_master; u8 lms = DWC_LLP_LMS(m_master); dma_addr_t reg; unsigned int reg_width; @@ -895,12 +895,7 @@ bool dw_dma_filter(struct dma_chan *chan, void *param) return false; /* We have to copy data since dws can be temporary storage */ - - dwc->src_id = dws->src_id; - dwc->dst_id = dws->dst_id; - - dwc->m_master = dws->m_master; - dwc->p_master = dws->p_master; + memcpy(&dwc->dws, dws, sizeof(struct dw_dma_slave)); return true; } @@ -1167,11 +1162,7 @@ static void dwc_free_chan_resources(struct dma_chan *chan) spin_lock_irqsave(&dwc->lock, flags); /* Clear custom channel configuration */ - dwc->src_id = 0; - dwc->dst_id = 0; - - dwc->m_master = 0; - dwc->p_master = 0; + memset(&dwc->dws, 0, sizeof(struct dw_dma_slave)); clear_bit(DW_DMA_IS_INITIALIZED, &dwc->flags); @@ -1264,7 +1255,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, struct dw_cyclic_desc *retval = NULL; struct dw_desc *desc; struct dw_desc *last = NULL; - u8 lms = DWC_LLP_LMS(dwc->m_master); + u8 lms = DWC_LLP_LMS(dwc->dws.m_master); unsigned long was_cyclic; unsigned int reg_width; unsigned int periods; diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h index 4b7bd7834046..f65dd104479f 100644 --- a/drivers/dma/dw/regs.h +++ b/drivers/dma/dw/regs.h @@ -245,10 +245,7 @@ struct dw_dma_chan { bool nollp; /* custom slave configuration */ - u8 src_id; - u8 dst_id; - u8 m_master; - u8 p_master; + struct dw_dma_slave dws; /* configuration passed via .device_config */ struct dma_slave_config dma_sconfig; |