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| author |   Paolo Bonzini <pbonzini@redhat.com> | 2019-07-11 15:14:16 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2019-07-11 15:14:16 +0200 |
| commit | a45ff5994c9cde41af627c46abb9f32beae68943 (patch) | |
| tree | b726cc506ed1b01484f183ab2679cdd618e1e9b1 /drivers/dma/mediatek/mtk-cqdma.c | |
| parent | Documentation: virtual: Add toctree hooks (diff) | |
| parent | KVM: arm/arm64: Initialise host's MPIDRs by reading the actual register (diff) | |
| download | linux-dev-a45ff5994c9cde41af627c46abb9f32beae68943.tar.xz linux-dev-a45ff5994c9cde41af627c46abb9f32beae68943.zip | |
Merge tag 'kvm-arm-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD
KVM/arm updates for 5.3
- Add support for chained PMU counters in guests
- Improve SError handling
- Handle Neoverse N1 erratum #1349291
- Allow side-channel mitigation status to be migrated
- Standardise most AArch64 system register accesses to msr_s/mrs_s
- Fix host MPIDR corruption on 32bit
Diffstat (limited to 'drivers/dma/mediatek/mtk-cqdma.c')
| -rw-r--r-- | drivers/dma/mediatek/mtk-cqdma.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c index 814853842e29..723b11c190b3 100644 --- a/drivers/dma/mediatek/mtk-cqdma.c +++ b/drivers/dma/mediatek/mtk-cqdma.c @@ -225,7 +225,7 @@ static int mtk_cqdma_hard_reset(struct mtk_cqdma_pchan *pc) mtk_dma_set(pc, MTK_CQDMA_RESET, MTK_CQDMA_HARD_RST_BIT); mtk_dma_clr(pc, MTK_CQDMA_RESET, MTK_CQDMA_HARD_RST_BIT); - return mtk_cqdma_poll_engine_done(pc, false); + return mtk_cqdma_poll_engine_done(pc, true); } static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc, @@ -671,7 +671,7 @@ static void mtk_cqdma_free_chan_resources(struct dma_chan *c) mtk_dma_set(cvc->pc, MTK_CQDMA_FLUSH, MTK_CQDMA_FLUSH_BIT); /* wait for the completion of flush operation */ - if (mtk_cqdma_poll_engine_done(cvc->pc, false) < 0) + if (mtk_cqdma_poll_engine_done(cvc->pc, true) < 0) dev_err(cqdma2dev(to_cqdma_dev(c)), "cqdma flush timeout\n"); /* clear the flush bit and interrupt flag */ |