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| author |   Dmitry Osipenko <digetx@gmail.com> | 2019-05-30 00:43:55 +0300 |
|---|---|---|
| committer |   Vinod Koul <vkoul@kernel.org> | 2019-06-04 17:45:47 +0530 |
| commit | dc161064beb83c668e0f85766b92b1e7ed186e58 (patch) | |
| tree | 645d5816df6ad2fbcc9a51696a8f894e011a609d /drivers/dma/tegra20-apb-dma.c | |
| parent | dmaengine: fsl-qdma: Continue to clear register on error (diff) | |
| download | linux-dev-dc161064beb83c668e0f85766b92b1e7ed186e58.tar.xz linux-dev-dc161064beb83c668e0f85766b92b1e7ed186e58.zip | |
dmaengine: tegra-apb: Error out if DMA_PREP_INTERRUPT flag is unset
Apparently driver was never tested with DMA_PREP_INTERRUPT flag being
unset since it completely disables interrupt handling instead of skipping
the callbacks invocations, hence putting channel into unusable state.
The flag is always set by all of kernel drivers that use APB DMA, so let's
error out in otherwise case for consistency. It won't be difficult to
support that case properly if ever will be needed.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/dma/tegra20-apb-dma.c')
| -rw-r--r-- | drivers/dma/tegra20-apb-dma.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c index cf462b1abc0b..2c84a660ba36 100644 --- a/drivers/dma/tegra20-apb-dma.c +++ b/drivers/dma/tegra20-apb-dma.c @@ -988,8 +988,12 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg( csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT; } - if (flags & DMA_PREP_INTERRUPT) + if (flags & DMA_PREP_INTERRUPT) { csr |= TEGRA_APBDMA_CSR_IE_EOC; + } else { + WARN_ON_ONCE(1); + return NULL; + } apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1; @@ -1131,8 +1135,12 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic( csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT; } - if (flags & DMA_PREP_INTERRUPT) + if (flags & DMA_PREP_INTERRUPT) { csr |= TEGRA_APBDMA_CSR_IE_EOC; + } else { + WARN_ON_ONCE(1); + return NULL; + } apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1; |