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| author |   Tony Luck <tony.luck@intel.com> | 2017-03-09 01:45:39 +0800 |
|---|---|---|
| committer |   Borislav Petkov <bp@suse.de> | 2017-03-16 12:40:52 +0100 |
| commit | 5c71ad17f97e84d6d7e11a8e193d5d96890ed2ed (patch) | |
| tree | 7d5e145d88e365800aa38e54768c98df69f3e64f /drivers/edac/Kconfig | |
| parent | EDAC, i5000, i5400: Fix use of MTR_DRAM_WIDTH macro (diff) | |
| download | linux-dev-5c71ad17f97e84d6d7e11a8e193d5d96890ed2ed.tar.xz linux-dev-5c71ad17f97e84d6d7e11a8e193d5d96890ed2ed.zip | |
EDAC, pnd2_edac: Add new EDAC driver for Intel SoC platforms
Initial target for this driver is the Intel Apollo Lake platform and
Denverton micro-server, they use the same internal memory controller IP
called Pondicherry2.
Memory controller registers are not in PCI config space like earlier
Intel memory controllers. For Apollo Lake platform they are accessed via
a "side-band" interface, for Denverton micro-server they are access via
PCI config space and memory map I/O. This driver is for Apollo Lake and
Denverton, but only the Denverton is fully enabled while we wait for the
sideband driver.
Apollo lake driver and initial cut at Denverton driver by Tony Luck.
Extensive cleanup, refactoring and basic verification by Qiuxu Zhuo.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/20170308174539.14432-1-qiuxu.zhuo@intel.com
Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'drivers/edac/Kconfig')
| -rw-r--r-- | drivers/edac/Kconfig | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 82d85cce81f8..be3eac6ad54d 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -259,6 +259,15 @@ config EDAC_SKX Support for error detection and correction the Intel Skylake server Integrated Memory Controllers. +config EDAC_PND2 + tristate "Intel Pondicherry2" + depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL + help + Support for error detection and correction on the Intel + Pondicherry2 Integrated Memory Controller. This SoC IP is + first used on the Apollo Lake platform and Denverton + micro-server but may appear on others in the future. + config EDAC_MPC85XX tristate "Freescale MPC83xx / MPC85xx" depends on EDAC_MM_EDAC && FSL_SOC |