diff options
| author |   Niklas Söderlund <niklas.soderlund@ericsson.com> | 2011-12-09 13:12:15 -0300 |
|---|---|---|
| committer |   Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-03-21 15:22:49 -0300 |
| commit | df95e42e1f20a561f2fe0a632d5b8fd6c26f1bb9 (patch) | |
| tree | fb323ff0928be60180c0fa6e069111de9361bb4b /drivers/edac/i5100_edac.c | |
| parent | edac: i5100 fix erroneous define for M1Err (diff) | |
| download | linux-dev-df95e42e1f20a561f2fe0a632d5b8fd6c26f1bb9.tar.xz linux-dev-df95e42e1f20a561f2fe0a632d5b8fd6c26f1bb9.zip | |
edac: i5100 ack error detection register after each read
If I only ack the detection register after a error have been detected
I'm unable to reliably detect errors. I have verified this behavior
using both an error injection DIMM and software to inject errors.
I can't find any documentation supporting this behavior in Intel 5100
Memory Controller Hub Chipset, see 1. So this is all based on
experimentation.
[1] Intel® 5100 Memory Controller Hub Chipset
http://www.intel.com/content/dam/doc/datasheet/5100-
memory-controller-hub-chipset-datasheet.pdf
Signed-off-by: Niklas Söderlund <niklas.soderlund@ericsson.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/edac/i5100_edac.c')
| -rw-r--r-- | drivers/edac/i5100_edac.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/drivers/edac/i5100_edac.c b/drivers/edac/i5100_edac.c index ab2f90619821..2a6e7ff1f020 100644 --- a/drivers/edac/i5100_edac.c +++ b/drivers/edac/i5100_edac.c @@ -535,23 +535,20 @@ static void i5100_read_log(struct mem_ctl_info *mci, int chan, static void i5100_check_error(struct mem_ctl_info *mci) { struct i5100_priv *priv = mci->pvt_info; - u32 dw; - + u32 dw, dw2; pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw); if (i5100_ferr_nf_mem_any(dw)) { - u32 dw2; pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2); - if (dw2) - pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, - dw2); - pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw); i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw), i5100_ferr_nf_mem_any(dw), i5100_nerr_nf_mem_any(dw2)); + + pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, dw2); } + pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw); } /* The i5100 chipset will scrub the entire memory once, then |