diff options
| author |   Elliot Berman <eberman@codeaurora.org> | 2020-01-07 13:04:17 -0800 |
|---|---|---|
| committer |   Bjorn Andersson <bjorn.andersson@linaro.org> | 2020-01-07 22:14:19 -0800 |
| commit | 5dad8deee29b7a64854e8bceb90337fa4db610de (patch) | |
| tree | 898a7a4e4eddd8bccb3ff6b9a08d6e490a85a91f /drivers/firmware | |
| parent | firmware: qcom_scm-64: Move SMC register filling to qcom_scm_call_smccc (diff) | |
| download | linux-dev-5dad8deee29b7a64854e8bceb90337fa4db610de.tar.xz linux-dev-5dad8deee29b7a64854e8bceb90337fa4db610de.zip | |
firmware: qcom_scm-64: Improve SMC convention detection
Improve the calling convention detection to use
__qcom_scm_is_call_available() and not blindly assume 32-bit mode if
the checks fails. BUG() if neither 32-bit or 64-bit mode works.
Tested-by: Brian Masney <masneyb@onstation.org> # arm32
Tested-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Elliot Berman <eberman@codeaurora.org>
Link: https://lore.kernel.org/r/1578431066-19600-9-git-send-email-eberman@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'drivers/firmware')
| -rw-r--r-- | drivers/firmware/qcom_scm-64.c | 41 |
1 files changed, 27 insertions, 14 deletions
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index 3ae171a70f4c..6bc7f69254bc 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -336,21 +336,34 @@ int __qcom_scm_ocmem_unlock(struct device *dev, uint32_t id, uint32_t offset, void __qcom_scm_init(void) { - u64 cmd; - struct arm_smccc_res res; - u32 fnid = SCM_SMC_FNID(QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL); - - /* First try a SMC64 call */ - cmd = ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, - ARM_SMCCC_OWNER_SIP, fnid); - - arm_smccc_smc(cmd, QCOM_SCM_ARGS(1), cmd & (~BIT(ARM_SMCCC_TYPE_SHIFT)), - 0, 0, 0, 0, 0, &res); + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_INFO, + .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL, + .args[0] = SCM_SMC_FNID(QCOM_SCM_SVC_INFO, + QCOM_SCM_INFO_IS_CALL_AVAIL) | + (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT), + .arginfo = QCOM_SCM_ARGS(1), + .owner = ARM_SMCCC_OWNER_SIP, + }; + struct qcom_scm_res res; + int ret; - if (!res.a0 && res.a1) - qcom_smccc_convention = ARM_SMCCC_SMC_64; - else - qcom_smccc_convention = ARM_SMCCC_SMC_32; + qcom_smccc_convention = ARM_SMCCC_SMC_64; + // Device isn't required as there is only one argument - no device + // needed to dma_map_single to secure world + ret = qcom_scm_call_atomic(NULL, &desc, &res); + if (!ret && res.result[0] == 1) + goto out; + + qcom_smccc_convention = ARM_SMCCC_SMC_32; + ret = qcom_scm_call_atomic(NULL, &desc, &res); + if (!ret && res.result[0] == 1) + goto out; + + qcom_smccc_convention = -1; + BUG(); +out: + pr_info("QCOM SCM SMC Convention: %lld\n", qcom_smccc_convention); } bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral) |