diff options
| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2015-03-18 19:41:08 +0100 |
|---|---|---|
| committer |   Linus Walleij <linus.walleij@linaro.org> | 2015-03-26 10:19:10 +0100 |
| commit | 3dc1e6852115b3163e7dacc76bbcb78ccff29421 (patch) | |
| tree | 9e8837db1eeb22ce42bb33e61c890be8381b1c09 /drivers/gpio | |
| parent | gpio: rcar: Use local variable gpio_chip in gpio_rcar_probe() (diff) | |
| download | linux-dev-3dc1e6852115b3163e7dacc76bbcb78ccff29421.tar.xz linux-dev-3dc1e6852115b3163e7dacc76bbcb78ccff29421.zip | |
gpio: rcar: Add more register documentation
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/gpio')
| -rw-r--r-- | drivers/gpio/gpio-rcar.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index e67d578ac07c..d96166ca1b42 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -39,18 +39,18 @@ struct gpio_rcar_priv { struct irq_chip irq_chip; }; -#define IOINTSEL 0x00 -#define INOUTSEL 0x04 -#define OUTDT 0x08 -#define INDT 0x0c -#define INTDT 0x10 -#define INTCLR 0x14 -#define INTMSK 0x18 -#define MSKCLR 0x1c -#define POSNEG 0x20 -#define EDGLEVEL 0x24 -#define FILONOFF 0x28 -#define BOTHEDGE 0x4c +#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */ +#define INOUTSEL 0x04 /* General Input/Output Switching Register */ +#define OUTDT 0x08 /* General Output Register */ +#define INDT 0x0c /* General Input Register */ +#define INTDT 0x10 /* Interrupt Display Register */ +#define INTCLR 0x14 /* Interrupt Clear Register */ +#define INTMSK 0x18 /* Interrupt Mask Register */ +#define MSKCLR 0x1c /* Interrupt Mask Clear Register */ +#define POSNEG 0x20 /* Positive/Negative Logic Select Register */ +#define EDGLEVEL 0x24 /* Edge/level Select Register */ +#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */ +#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */ #define RCAR_MAX_GPIO_PER_BANK 32 |