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| author |   Lijo Lazar <lijo.lazar@amd.com> | 2021-03-08 13:57:17 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-03-23 23:01:51 -0400 |
| commit | 775f11aa17b14b97229642a87b95a1916d99a961 (patch) | |
| tree | ceef6fd66acf1671b68e182cde9c540a9c9575ac /drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | |
| parent | drm/amdgpu: Set GTT_USWC flag to enable freesync v2 (diff) | |
| download | linux-dev-775f11aa17b14b97229642a87b95a1916d99a961.tar.xz linux-dev-775f11aa17b14b97229642a87b95a1916d99a961.zip | |
drm/amd/pm: Enable pp_od_clk_voltage node on aldebaran
Use pp_od_clk_voltage node to enable performance determinism and GFX
clock min/max range for aldebaran. This is to avoid overload of
pp_dpm_sclk and maintain consistency in user lib interfaces.
Ex: To enable perf determinism at 900MHz max gfx clock
1) echo perf_determinism > /sys/bus/pci/devices/.../power_dpm_force_performance_level
2) echo s 1 900 > /sys/bus/pci/devices/.../pp_od_clk_voltage
3) echo c > /sys/bus/pci/devices/.../pp_od_clk_voltage
Ex: To enable min 500MHz/max 900MHz gfx clocks
1) echo manual > "/sys/bus/pci/devices/.../power_dpm_force_performance_level"
2) echo s 0 500 > "/sys/bus/pci/devices/.../pp_od_clk_voltage"
3) echo s 1 900 > "/sys/bus/pci/devices/.../pp_od_clk_voltage”
4) echo c > "/sys/bus/pci/devices/.../pp_od_clk_voltage”
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c')
0 files changed, 0 insertions, 0 deletions