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| author |   Jack Xiao <Jack.Xiao@amd.com> | 2015-05-08 14:46:49 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2015-06-03 21:03:28 -0400 |
| commit | 74a5d1656e165d5457be64b4d78d3259c2946e93 (patch) | |
| tree | 968ada5f776dead7d0ec398443b84bcb2237f875 /drivers/gpu/drm/amd/amdgpu/cik_sdma.c | |
| parent | drm/amdgpu: make the CTX ioctl thread-safe (diff) | |
| download | linux-dev-74a5d1656e165d5457be64b4d78d3259c2946e93.tar.xz linux-dev-74a5d1656e165d5457be64b4d78d3259c2946e93.zip | |
drm/amdgpu: allow unaligned memory access (v2)
Set up the CP and SDMA for proper unaligned memory access.
Required for OpenCL 2.x
v2: udpate commit message
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/cik_sdma.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index ae2bb26fa46e..037e3db69547 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -33,6 +33,8 @@ #include "bif/bif_4_1_sh_mask.h" #include "gca/gfx_7_2_d.h" +#include "gca/gfx_7_2_enum.h" +#include "gca/gfx_7_2_sh_mask.h" #include "gmc/gmc_7_1_d.h" #include "gmc/gmc_7_1_sh_mask.h" @@ -837,6 +839,8 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, { u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ + u32 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, + SH_MEM_ALIGNMENT_MODE_UNALIGNED); amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); if (vm_id < 8) { @@ -857,7 +861,7 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); amdgpu_ring_write(ring, mmSH_MEM_CONFIG); - amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, sh_mem_cfg); amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE); |