diff options
| author |   Alex Deucher <alexander.deucher@amd.com> | 2017-06-07 14:20:21 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-06-07 18:20:58 -0400 |
| commit | 4853bbb6fbb9429b84ddd3562c7f2967ca880d03 (patch) | |
| tree | f89fba4f9441974ea60ffbcad73b871594d398a8 /drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | |
| parent | drm/amdgpu/gfx: move more common KIQ code to amdgpu_gfx.c (diff) | |
| download | linux-dev-4853bbb6fbb9429b84ddd3562c7f2967ca880d03.tar.xz linux-dev-4853bbb6fbb9429b84ddd3562c7f2967ca880d03.zip | |
drm/amdgpu/gfx: move mec parameter setup into sw_init
This will allow us to share more mec code.
Reviewed-by: Alex Xie <AlexBin.Xie@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index d80cf72f6922..e30c7d0bd0f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2817,21 +2817,6 @@ static int gfx_v7_0_mec_init(struct amdgpu_device *adev) bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); - switch (adev->asic_type) { - case CHIP_KAVERI: - adev->gfx.mec.num_mec = 2; - break; - case CHIP_BONAIRE: - case CHIP_HAWAII: - case CHIP_KABINI: - case CHIP_MULLINS: - default: - adev->gfx.mec.num_mec = 1; - break; - } - adev->gfx.mec.num_pipe_per_mec = 4; - adev->gfx.mec.num_queue_per_pipe = 8; - /* take ownership of the relevant compute queues */ amdgpu_gfx_compute_queue_acquire(adev); @@ -4723,6 +4708,21 @@ static int gfx_v7_0_sw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; int i, j, k, r, ring_id; + switch (adev->asic_type) { + case CHIP_KAVERI: + adev->gfx.mec.num_mec = 2; + break; + case CHIP_BONAIRE: + case CHIP_HAWAII: + case CHIP_KABINI: + case CHIP_MULLINS: + default: + adev->gfx.mec.num_mec = 1; + break; + } + adev->gfx.mec.num_pipe_per_mec = 4; + adev->gfx.mec.num_queue_per_pipe = 8; + /* EOP Event */ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); if (r) |