diff options
| author |   Le Ma <le.ma@amd.com> | 2018-08-31 14:17:28 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-07-18 14:18:01 -0500 |
| commit | 1daa2bfa17aa5ace20bb02509cd3d2c2c0afc642 (patch) | |
| tree | 3a3bd16445d0b04f761b82b5a4ebf6cc3d8b3b9a /drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | |
| parent | drm/amdgpu: rename AMDGPU_GFXHUB/MMHUB macro with hub number (diff) | |
| download | linux-dev-1daa2bfa17aa5ace20bb02509cd3d2c2c0afc642.tar.xz linux-dev-1daa2bfa17aa5ace20bb02509cd3d2c2c0afc642.zip | |
drm/amdgpu: add new member in amdgpu_device for vmhub counts per asic chip
It aims to replace AMDGPU_MAX_VMHUBS in for loop to initialize registers.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index ad45d633b147..2afc37237ad3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -284,7 +284,7 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) { + for (j = 0; j < adev->num_vmhubs; j++) { hub = &adev->vmhub[j]; for (i = 0; i < 16; i++) { reg = hub->vm_context0_cntl + i; @@ -295,7 +295,7 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, } break; case AMDGPU_IRQ_STATE_ENABLE: - for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) { + for (j = 0; j < adev->num_vmhubs; j++) { hub = &adev->vmhub[j]; for (i = 0; i < 16; i++) { reg = hub->vm_context0_cntl + i; @@ -419,7 +419,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, const unsigned eng = 17; unsigned i, j; - for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { + for (i = 0; i < adev->num_vmhubs; ++i) { struct amdgpu_vmhub *hub = &adev->vmhub[i]; u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type); @@ -980,6 +980,8 @@ static int gmc_v9_0_sw_init(void *handle) adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); switch (adev->asic_type) { case CHIP_RAVEN: + adev->num_vmhubs = 2; + if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); } else { @@ -992,6 +994,8 @@ static int gmc_v9_0_sw_init(void *handle) case CHIP_VEGA10: case CHIP_VEGA12: case CHIP_VEGA20: + adev->num_vmhubs = 2; + /* * To fulfill 4-level page support, * vm size is 256TB (48bit), maximum size of Vega10, |