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authorDave Airlie <airlied@redhat.com>2017-05-12 13:58:29 +1000
committerDave Airlie <airlied@redhat.com>2017-05-12 13:58:29 +1000
commit7ec27233e62b5efe795563896577de5340dc7473 (patch)
tree7cf654cf27518d5e0b1a7718ad454fa3a5d45af8 /drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h
parentMerge tag 'drm-misc-next-fixes-2017-05-05' of git://anongit.freedesktop.org/git/drm-misc into drm-next (diff)
parentdrm/amd/powerplay: refine pwm1_enable callback functions for CI. (diff)
downloadlinux-dev-7ec27233e62b5efe795563896577de5340dc7473.tar.xz
linux-dev-7ec27233e62b5efe795563896577de5340dc7473.zip
Merge branch 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux into drm-next
Fixes for 4.12. This is a bit bigger than usual since it's 3 weeks worth of fixes and most of these changes are for vega10 which is new for 4.12 and still in a fair amount of flux. It looks like you missed my last pull request, so those patches are included here as well. Highlights: - Lots of vega10 fixes - Fix interruptable wait mixup - Fan control method fixes - Misc display fixes for radeon and amdgpu - Misc bug fixes * 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux: (132 commits) drm/amd/powerplay: refine pwm1_enable callback functions for CI. drm/amd/powerplay: refine pwm1_enable callback functions for vi. drm/amd/powerplay: refine pwm1_enable callback functions for Vega10. drm/amdgpu: refine amdgpu pwm1_enable sysfs interface. drm/amdgpu: add amd fan ctrl mode enums. drm/amd/powerplay: add more smu message on Vega10. drm/amdgpu: fix dependency issue drm/amd: fix init order of sched job drm/amdgpu: add some additional vega10 pci ids drm/amdgpu/soc15: use atomfirmware for setting bios scratch for reset drm/amdgpu/atomfirmware: add function to update engine hang status drm/radeon: only warn once in radeon_ttm_bo_destroy if va list not empty drm/amdgpu: fix mutex list null pointer reference drm/amd/powerplay: fix bug sclk/mclk level can't be set on vega10. drm/amd/powerplay: Setup sw CTF to allow graceful exit when temperature exceeds maximum. drm/amd/powerplay: delete dead code in powerplay. drm/amdgpu: Use less generic enum definitions drm/amdgpu/gfx9: derive tile pipes from golden settings drm/amdgpu/gfx: drop max_gs_waves_per_vgt drm/amd/powerplay: disable engine spread spectrum feature on Vega10. ...
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h57
1 files changed, 57 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h b/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h
index 5f0fc8bf16a9..8af0bddf85e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h
@@ -84,4 +84,61 @@ struct mmsch_v1_0_cmd_indirect_write {
uint32_t reg_value;
};
+static inline void mmsch_v1_0_insert_direct_wt(struct mmsch_v1_0_cmd_direct_write *direct_wt,
+ uint32_t *init_table,
+ uint32_t reg_offset,
+ uint32_t value)
+{
+ direct_wt->cmd_header.reg_offset = reg_offset;
+ direct_wt->reg_value = value;
+ memcpy((void *)init_table, direct_wt, sizeof(struct mmsch_v1_0_cmd_direct_write));
+}
+
+static inline void mmsch_v1_0_insert_direct_rd_mod_wt(struct mmsch_v1_0_cmd_direct_read_modify_write *direct_rd_mod_wt,
+ uint32_t *init_table,
+ uint32_t reg_offset,
+ uint32_t mask, uint32_t data)
+{
+ direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;
+ direct_rd_mod_wt->mask_value = mask;
+ direct_rd_mod_wt->write_data = data;
+ memcpy((void *)init_table, direct_rd_mod_wt,
+ sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write));
+}
+
+static inline void mmsch_v1_0_insert_direct_poll(struct mmsch_v1_0_cmd_direct_polling *direct_poll,
+ uint32_t *init_table,
+ uint32_t reg_offset,
+ uint32_t mask, uint32_t wait)
+{
+ direct_poll->cmd_header.reg_offset = reg_offset;
+ direct_poll->mask_value = mask;
+ direct_poll->wait_value = wait;
+ memcpy((void *)init_table, direct_poll, sizeof(struct mmsch_v1_0_cmd_direct_polling));
+}
+
+#define MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
+ mmsch_v1_0_insert_direct_rd_mod_wt(&direct_rd_mod_wt, \
+ init_table, (reg), \
+ (mask), (data)); \
+ init_table += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; \
+ table_size += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; \
+}
+
+#define MMSCH_V1_0_INSERT_DIRECT_WT(reg, value) { \
+ mmsch_v1_0_insert_direct_wt(&direct_wt, \
+ init_table, (reg), \
+ (value)); \
+ init_table += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \
+ table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \
+}
+
+#define MMSCH_V1_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
+ mmsch_v1_0_insert_direct_poll(&direct_poll, \
+ init_table, (reg), \
+ (mask), (wait)); \
+ init_table += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \
+ table_size += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \
+}
+
#endif