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| author |   Tao Zhou <tao.zhou1@amd.com> | 2019-05-14 11:37:32 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-06-21 18:59:31 -0500 |
| commit | 462a70d87e257aa26a528b210775fa58f5417e0a (patch) | |
| tree | 242fe787d01ed068d156b17bfdc95eb89bfe2794 /drivers/gpu/drm/amd/amdgpu/nv.c | |
| parent | drm/amd/powerplay/smu11: disable some pp features on navi10 A0 secure board (diff) | |
| download | linux-dev-462a70d87e257aa26a528b210775fa58f5417e0a.tar.xz linux-dev-462a70d87e257aa26a528b210775fa58f5417e0a.zip | |
drm/amdgpu: correct reference clock value on navi10
remove the divisor 4
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/nv.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nv.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index ae3a407b16a3..a3692dba64ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -122,7 +122,7 @@ static u32 nv_get_config_memsize(struct amdgpu_device *adev) static u32 nv_get_xclk(struct amdgpu_device *adev) { - return adev->clock.spll.reference_freq / 4; + return adev->clock.spll.reference_freq; } |