drm/amdgpu: convert IP version array to include instances

Allow us to query instances versions more cleanly.

Instancing support is not consistent unfortunately. SDMA is a
good example.  Sienna cichlid has 4 total SDMA instances, each
enumerated separately (HWIDs 42, 43, 68, 69).  Arcturus has 8
total SDMA instances, but they are enumerated as multiple
instances of the same HWIDs (4x HWID 42, 4x HWID 43).  UMC
is another example.  On most chips there are multiple
instances with the same HWID.  This allows us to support both
forms.

v2: rebase
v3: clarify instancing support

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 12 insertions, 12 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 204e491cc5d2..0640e143e7a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -156,8 +156,8 @@ static const struct amdgpu_video_codecs rn_video_codecs_decode =
 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
 				    const struct amdgpu_video_codecs **codecs)
 {
-	if (adev->ip_versions[VCE_HWIP]) {
-		switch (adev->ip_versions[VCE_HWIP]) {
+	if (adev->ip_versions[VCE_HWIP][0]) {
+		switch (adev->ip_versions[VCE_HWIP][0]) {
 		case IP_VERSION(4, 0, 0):
 		case IP_VERSION(4, 1, 0):
 			if (encode)
@@ -169,7 +169,7 @@ static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
 			return -EINVAL;
 		}
 	} else {
-		switch (adev->ip_versions[UVD_HWIP]) {
+		switch (adev->ip_versions[UVD_HWIP][0]) {
 		case IP_VERSION(1, 0, 0):
 		case IP_VERSION(1, 0, 1):
 			if (encode)
@@ -341,11 +341,11 @@ static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
 	u32 reference_clock = adev->clock.spll.reference_freq;
 
-	if (adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 0) ||
-	    adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 1))
+	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) ||
+	    adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1))
 		return 10000;
-	if (adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 0) ||
-	    adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 1))
+	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) ||
+	    adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1))
 		return reference_clock / 4;
 
 	return reference_clock;
@@ -576,7 +576,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
 		dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 				  amdgpu_reset_method);
 
-	switch (adev->ip_versions[MP1_HWIP]) {
+	switch (adev->ip_versions[MP1_HWIP][0]) {
 	case IP_VERSION(10, 0, 0):
 	case IP_VERSION(10, 0, 1):
 	case IP_VERSION(12, 0, 0):
@@ -641,7 +641,7 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
 
 static bool soc15_supports_baco(struct amdgpu_device *adev)
 {
-	switch (adev->ip_versions[MP1_HWIP]) {
+	switch (adev->ip_versions[MP1_HWIP][0]) {
 	case IP_VERSION(9, 0, 0):
 	case IP_VERSION(11, 0, 2):
 		if (adev->asic_type == CHIP_VEGA20) {
@@ -1172,7 +1172,7 @@ static int soc15_common_early_init(void *handle)
 	/* TODO: split the GC and PG flags based on the relevant IP version for which
 	 * they are relevant.
 	 */
-	switch (adev->ip_versions[GC_HWIP]) {
+	switch (adev->ip_versions[GC_HWIP][0]) {
 	case IP_VERSION(9, 0, 1):
 		adev->asic_funcs = &soc15_asic_funcs;
 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
@@ -1582,7 +1582,7 @@ static int soc15_common_set_clockgating_state(void *handle,
 	if (amdgpu_sriov_vf(adev))
 		return 0;
 
-	switch (adev->ip_versions[NBIO_HWIP]) {
+	switch (adev->ip_versions[NBIO_HWIP][0]) {
 	case IP_VERSION(6, 1, 0):
 	case IP_VERSION(6, 2, 0):
 	case IP_VERSION(7, 4, 0):
@@ -1638,7 +1638,7 @@ static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
 
 	adev->hdp.funcs->get_clock_gating_state(adev, flags);
 
-	if (adev->ip_versions[MP0_HWIP] != IP_VERSION(13, 0, 2)) {
+	if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) {
 
 		/* AMD_CG_SUPPORT_DRM_MGCG */
 		data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));