Merge tag 'drm-for-v4.12' of git://people.freedesktop.org/~airlied/linux

Pull drm u pdates from Dave Airlie:
 "This is the main drm pull request for v4.12. Apart from two fixes
  pulls, everything should have been in drm-next for at least 2 weeks.

  The biggest thing in here is AMD released the public headers for their
  upcoming VEGA GPUs. These as always are quite a sizeable chunk of
  header files. They've also added initial non-display support for those
  GPUs, though they aren't available in production yet.

  Otherwise it's pretty much normal.

  New bridge drivers:
   - megachips-stdpxxxx-ge-b850v3-fw LVDS->DP++
   - generic LVDS bridge support.

  Core:
   - Displayport link train failure reporting to userspace
   - debugfs interface cleaned up
   - subsystem TODO in kerneldoc now
   - Extended fbdev support (flipping and vblank wait)
   - drm_platform removed
   - EDP CRC support in helper
   - HF-VSDB SCDC support in EDID parser
   - Lots of code cleanups and header extraction
   - Thunderbolt external GPU awareness
   - Atomic helper improvements
   - Documentation improvements

  panel:
   - Sitronix and Samsung new panel support

  amdgpu:
   - Preliminary vega10 support
   - Multi-level page table support
   - GPU sensor support for userspace
   - PRT support for sparse buffers
   - SR-IOV improvements
   - Non-contig VRAM CPU mapping

  i915:
   - Atomic modesetting enabled by default on Gen5+
   - LSPCON improvements
   - Atomic state handling for cdclk
   - GPU reset improvements
   - In-kernel unit tests
   - Geminilake improvements and color manager support
   - Designware i2c fixes
   - vblank evasion improvements
   - Hotplug safe connector iterators
   - GVT scheduler QoS support
   - GVT Kabylake support

  nouveau:
   - Acceleration support for Pascal (GP10x).
   - Rearchitecture of code handling proprietary signed firmware
   - Fix GTX 970 with odd MMU configuration
   - GP10B support
   - GP107 acceleration support

  vmwgfx:
   - Atomic modesetting support for vmwgfx

  omapdrm:
   - Support for render nodes
   - Refactor omapdss code
   - Fix some probe ordering issues
   - Fix too dark RGB565 rendering

  sunxi:
   - prelim rework for multiple pipes.

  mali-dp:
   - Color management support
   - Plane scaling
   - Power management improvements

  imx-drm:
   - Prefetch Resolve Engine/Gasket on i.MX6QP
   - Deferred plane disabling
   - Separate alpha support

  mediatek:
   - Mediatek SoC MT2701 support

  rcar-du:
   - Gen3 HDMI support

  msm:
   - 4k support for newer chips
   - OPP bindings for gpu
   - prep work for per-process pagetables

  vc4:
   - HDMI audio support
   - fixes

  qxl:
   - minor fixes.

  dw-hdmi:
   - PHY improvements
   - CSC fixes
   - Amlogic GX SoC support"

* tag 'drm-for-v4.12' of git://people.freedesktop.org/~airlied/linux: (1778 commits)
  drm/nouveau/fb/gf100-: Fix 32 bit wraparound in new ram detection
  drm/nouveau/secboot/gm20b: fix the error return code in gm20b_secboot_tegra_read_wpr()
  drm/nouveau/kms: Increase max retries in scanout position queries.
  drm/nouveau/bios/bitP: check that table is long enough for optional pointers
  drm/nouveau/fifo/nv40: no ctxsw for pre-nv44 mpeg engine
  drm: mali-dp: use div_u64 for expensive 64-bit divisions
  drm/i915: Confirm the request is still active before adding it to the await
  drm/i915: Avoid busy-spinning on VLV_GLTC_PW_STATUS mmio
  drm/i915/selftests: Allocate inode/file dynamically
  drm/i915: Fix system hang with EI UP masked on Haswell
  drm/i915: checking for NULL instead of IS_ERR() in mock selftests
  drm/i915: Perform link quality check unconditionally during long pulse
  drm/i915: Fix use after free in lpe_audio_platdev_destroy()
  drm/i915: Use the right mapping_gfp_mask for final shmem allocation
  drm/i915: Make legacy cursor updates more unsynced
  drm/i915: Apply a cond_resched() to the saturated signaler
  drm/i915: Park the signaler before sleeping
  drm: mali-dp: Check the mclk rate and allow up/down scaling
  drm: mali-dp: Enable image enhancement when scaling
  drm: mali-dp: Add plane upscaling support
  ...

1 files changed, 0 insertions, 112 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
index 719587b8b0cb..575d7aed5d32 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.h
+++ b/drivers/gpu/drm/amd/amdgpu/vi.h
@@ -28,116 +28,4 @@ void vi_srbm_select(struct amdgpu_device *adev,
 		    u32 me, u32 pipe, u32 queue, u32 vmid);
 int vi_set_ip_blocks(struct amdgpu_device *adev);
 
-struct amdgpu_ce_ib_state
-{
-	uint32_t    ce_ib_completion_status;
-	uint32_t    ce_constegnine_count;
-	uint32_t    ce_ibOffset_ib1;
-	uint32_t    ce_ibOffset_ib2;
-}; /* Total of 4 DWORD */
-
-struct amdgpu_de_ib_state
-{
-	uint32_t    ib_completion_status;
-	uint32_t    de_constEngine_count;
-	uint32_t    ib_offset_ib1;
-	uint32_t    ib_offset_ib2;
-	uint32_t    preamble_begin_ib1;
-	uint32_t    preamble_begin_ib2;
-	uint32_t    preamble_end_ib1;
-	uint32_t    preamble_end_ib2;
-	uint32_t    draw_indirect_baseLo;
-	uint32_t    draw_indirect_baseHi;
-	uint32_t    disp_indirect_baseLo;
-	uint32_t    disp_indirect_baseHi;
-	uint32_t    gds_backup_addrlo;
-	uint32_t    gds_backup_addrhi;
-	uint32_t    index_base_addrlo;
-	uint32_t    index_base_addrhi;
-	uint32_t    sample_cntl;
-}; /* Total of 17 DWORD */
-
-struct amdgpu_ce_ib_state_chained_ib
-{
-	/* section of non chained ib part */
-	uint32_t    ce_ib_completion_status;
-	uint32_t    ce_constegnine_count;
-	uint32_t    ce_ibOffset_ib1;
-	uint32_t    ce_ibOffset_ib2;
-
-	/* section of chained ib */
-	uint32_t    ce_chainib_addrlo_ib1;
-	uint32_t    ce_chainib_addrlo_ib2;
-	uint32_t    ce_chainib_addrhi_ib1;
-	uint32_t    ce_chainib_addrhi_ib2;
-	uint32_t    ce_chainib_size_ib1;
-	uint32_t    ce_chainib_size_ib2;
-}; /* total 10 DWORD */
-
-struct amdgpu_de_ib_state_chained_ib
-{
-	/* section of non chained ib part */
-	uint32_t    ib_completion_status;
-	uint32_t    de_constEngine_count;
-	uint32_t    ib_offset_ib1;
-	uint32_t    ib_offset_ib2;
-
-	/* section of chained ib */
-	uint32_t    chain_ib_addrlo_ib1;
-	uint32_t    chain_ib_addrlo_ib2;
-	uint32_t    chain_ib_addrhi_ib1;
-	uint32_t    chain_ib_addrhi_ib2;
-	uint32_t    chain_ib_size_ib1;
-	uint32_t    chain_ib_size_ib2;
-
-	/* section of non chained ib part */
-	uint32_t    preamble_begin_ib1;
-	uint32_t    preamble_begin_ib2;
-	uint32_t    preamble_end_ib1;
-	uint32_t    preamble_end_ib2;
-
-	/* section of chained ib */
-	uint32_t    chain_ib_pream_addrlo_ib1;
-	uint32_t    chain_ib_pream_addrlo_ib2;
-	uint32_t    chain_ib_pream_addrhi_ib1;
-	uint32_t    chain_ib_pream_addrhi_ib2;
-
-	/* section of non chained ib part */
-	uint32_t    draw_indirect_baseLo;
-	uint32_t    draw_indirect_baseHi;
-	uint32_t    disp_indirect_baseLo;
-	uint32_t    disp_indirect_baseHi;
-	uint32_t    gds_backup_addrlo;
-	uint32_t    gds_backup_addrhi;
-	uint32_t    index_base_addrlo;
-	uint32_t    index_base_addrhi;
-	uint32_t    sample_cntl;
-}; /* Total of 27 DWORD */
-
-struct amdgpu_gfx_meta_data
-{
-	/* 4 DWORD, address must be 4KB aligned */
-	struct amdgpu_ce_ib_state    ce_payload;
-	uint32_t                     reserved1[60];
-	/* 17 DWORD, address must be 64B aligned */
-	struct amdgpu_de_ib_state    de_payload;
-	/* PFP IB base address which get pre-empted */
-	uint32_t                     DeIbBaseAddrLo;
-	uint32_t                     DeIbBaseAddrHi;
-	uint32_t                     reserved2[941];
-}; /* Total of 4K Bytes */
-
-struct amdgpu_gfx_meta_data_chained_ib
-{
-	/* 10 DWORD, address must be 4KB aligned */
-	struct amdgpu_ce_ib_state_chained_ib   ce_payload;
-	uint32_t                               reserved1[54];
-	/* 27 DWORD, address must be 64B aligned */
-	struct amdgpu_de_ib_state_chained_ib   de_payload;
-	/* PFP IB base address which get pre-empted */
-	uint32_t                               DeIbBaseAddrLo;
-	uint32_t                               DeIbBaseAddrHi;
-	uint32_t                               reserved2[931];
-}; /* Total of 4K Bytes */
-
 #endif